Processors, methods and systems to allow secure communications between protected container memory and input/output devices

1. An integrated circuit comprising:

a decode unit to decode an instruction;

an execution unit coupled with the decode unit to perform operations corresponding to the instruction; and

a protected container access control circuitry, coupled with the execution unit, the protected container access control circuitry to perform a set of access control checks associated with the instruction and to determine whether to allow a device protected container module (DPCM) and an input and/or output (I/O) device to communicate securely through one of direct memory access (DMA) and memory-mapped input/output (MMIO), wherein the protected container access control circuitry is to determine to allow the DPCM and the I/O device to said communicate securely if the set of access control checks determine that at least:

the DPCM and the I/O device are mapped to one another;

an access address used to said communicate securely resolves into a protected container memory;

the access address matches an allowed physical address that is to be retrieved from a protected control structure; and

a page of the protected container memory into which the access address resolves allows for said one of DMA and MMIO.

2. The integrated circuit of claim 1 , wherein said one of the DMA and the MMIO is the DMA.

3. The integrated circuit of claim 2 , wherein the protected container access control circuitry is to determine to allow and allow the I/O device to access the page of the protected container memory.

4. The integrated circuit of claim 2 , wherein the access address is associated with a Security Attributes of Initiator (SAI) corresponding to the I/O device, and wherein the protected container access control circuitry is to determine that the DPCM and the I/O device are mapped to one another by using the SAI of the I/O device to obtain a DPCM identifier mapped to the SAI of the I/O device in a device mapping table and determine that the DPCM identifier obtained from the table corresponds to the DPCM.

5. The integrated circuit of claim 1 , wherein the decode unit is to decode a second instruction, and wherein the execution unit, in response to the second instruction, to store the allowed physical address in the protected control structure.

6. The integrated circuit of claim 2 , wherein the protected container access control circuitry is to determine to allow and allow the DPCM and the I/O device to communicate securely after it has been determined that the page has a type that is dedicated to allowing secure DMA.

7. The integrated circuit of claim 2 , wherein the protected container access control circuitry comprises an I/O memory management unit (MMU).

8. The integrated circuit of claim 1 , wherein said one of the DMA and the MMIO is the MMIO.

9. The integrated circuit of claim 8 , further comprising a memory management unit (MMU) to convert an address that resolves into the page of the protected container memory to an MMIO address for the I/O device.

10. The integrated circuit of claim 8 , wherein the protected container access control circuitry is to provide a security identifier to accompany an access from the DPCM to the I/O device, and wherein the security identifier is to attest to the I/O device that the access is from a DPCM that is mapped to the I/O device.

11. The integrated circuit of claim 8 , wherein the protected container access control circuitry is to determine to allow and allow the DPCM and the I/O device to communicate securely after a determination that the page has a type that is dedicated to allowing secure MMIO.

12. The integrated circuit of claim 8 , wherein the protected container access control circuitry comprises a memory management unit (MMU).

13. The integrated circuit of claim 1 , wherein the protected container access control circuitry is to determine to allow and allow the DPCM and the I/O device to communicate securely after a determination that a type of access is compatible with one or more allowed access types for the page that are to be stored in a protected container page metadata structure.

14. The integrated circuit of claim 1 , wherein the protected container access control circuitry is not to allow:

any other protected container modules to access the page of the protected container memory; and

any privileged system software modules to access the page of the protected container memory.

15. A method comprising:

determining that a set of access control checks succeed, including:

determining that a device protected container module (DPCM) and an input and/or output (I/O) device are mapped to one another;

determining that an access address associated with an attempted access by one of the DPCM and the I/O device resolves into a protected container memory;

determining that the access address matches an allowed physical address retrieved from a protected control structure; and

determining that a page of the protected container memory into which the access address resolves allows for one of direct memory access (DMA) and memory-mapped input/output (MMIO); and

after said determining that the set of access control checks succeed, allowing the DPCM and the I/O device to communicate securely with one another through the page of the protected container memory.

16. The method of claim 15 , wherein said allowing the DPCM and the I/O device to communicate securely with one another comprises allowing the DPCM and the I/O device to perform secure DMA, the method further comprising allowing the I/O device to access data in the page of the protected container memory.

17. The method of claim 15 , wherein said allowing the DPCM and the I/O device to communicate securely with one another comprises allowing the DPCM and the I/O device to perform secure MMIO.

18. A system comprising:

a memory to store a device protected container module (DPCM);

an input and/or output (I/O) device to interface with a privileged-level portion of the DPCM; and

a processor coupled with the memory and the I/O device, the processor to perform instructions of a protected container, the protected container to interface with a user-level portion of the DPCM, the processor to perform a set of access control checks to determine whether to allow the DPCM and the I/O device to communicate securely through one of direct memory access (DMA) and memory-mapped input/output (MMIO) after (MMIO), wherein the processor is to determine to allow the DPCM and the I/O device to said communicate securely if the set of access control checks determine that it has been determined that at least:

the DPCM and the I/O device are mapped to one another;

an access address used to said communicate securely resolves into a protected container memory; and

a page of the protected container memory into which the access address resolves allows for said one of DMA and MMIO.

19. The system of claim 18 , wherein the processor is to determine to allow the DPCM and the I/O device to said communicate securely if the set of access control checks determine that the access address matches an allowed physical address that is to be retrieved from a protected control structure.