Neural network apparatus and method of processing variable-resolution operation by the same

1. A neural network apparatus that processes an operation, the neural network apparatus comprising:

neural network circuitry configured to,

map i and j such that an ith bit of an n-bit activation and a jth bit of an m-bit weight are differently combined for respective instances of performing the operation, wherein n is a natural number and i is a natural number between 1 and n inclusive, and wherein m is a natural number and j is a natural number between 1 and m inclusive;

receive, for each of the respective instances, a first input corresponding to the i th bit of the n-bit activation;

store, for each of the respective instances, a second input corresponding the i th bit of the m-bit weight;

perform, for each of the respective instances, a determination whether the operation is to be performed on the i th bit and the j th bit; and

based on the determination being a positive determination,

perform the operation on the i th bit and the j th bit, and

produce each bit of an operation value of the operation performed on the i th bit and the j th bit based on the determination.

2. The neural network apparatus of claim 1 ,

wherein the neural network circuitry is configured to perform the determination based on whether another operation may be influenced by whether the operation is performed on, as an input, the operation value of the operation, and

wherein the determination is a negative determination based on the another operation not being influenced by the operation value of the operation.

3. The neural network apparatus of claim 2 , wherein,

the operation includes an arithmetic operation,

the neural network circuitry is configured to not perform the arithmetic operation when the determination is the negative determination, and

the neural network circuitry is configured to produce the operation value of the operation including an arithmetic value and a carry value by performing the operation on the i th bit and the j th bit based on the determination.

4. The neural network apparatus of claim 1 , wherein the neural network circuitry is configured to,

receive a set of received values including at least one of,

a predetermined initial value,

a first operation value produced at a previous point of time,

a second operation value produced at a current point of time,

an arithmetic value produced by the neural network circuitry at the previous point of time, and

a carry value produced by the neural network circuitry at the previous point of time, and

perform the determination as,

a negative determination based on the received values are the same as the first operation value, and

the positive determination based on any one of the received values being the same as the second operation value.

5. The neural network apparatus of claim 1 , wherein the neural network circuitry further comprises a full adder configured to perform the operation on, as inputs, a predetermined initial value, a first operation value produced by the neural network circuitry at a previous point of time, a second operation value produced by the neural network circuitry at a current point of time, an arithmetic value produced by the neural network circuitry at the previous point of time, and a carry value produced by the neural network circuitry at the previous point of time.

6. The neural network apparatus of claim 1 , wherein at least one of an arithmetic value or a carry value produced by the neural network circuitry corresponds to a bit value of a set of bits produced by the operation.

7. The neural network apparatus of claim 1 , wherein, after a bit of the operation value of the operation is produced, the neural network circuitry is configured to perform the operation again to produce another bit of the operation value of the operation.

8. The neural network apparatus of claim 1 , wherein the neural network circuitry is further configured to determine the first input corresponding to the i th bit and the second input corresponding to the j th bit to sequentially obtain a lower bit value to an upper bit value of the operation value of the operation.

9. The neural network apparatus of claim 1 , wherein the neural network circuitry is further configured to choose i and j such that combinations, ranging from a combination of the i th bit and the j th bit such that a sum of i and j is smallest to a combination of the i th bit and the j th bit such that a sum of i and j is largest, are sequentially performed by the neural network circuitry.

10. A method of processing an operation by a neural network apparatus, the method comprising:

determining a first input corresponding to an i th bit of an n-bit activation, and a second input corresponding to a j th bit of an m-bit weight;

performing a determination whether the operation is to be performed on the first input and the second input, and produce a positive determination or a negative determination as a result of the determination; and

performing the operation on the first input and the second input to produce an operation value of the operation based on the positive determination,

wherein n and m are natural numbers, i is a natural number between 1 and n inclusive, and j is a natural number between 1 and m inclusive, and

wherein producing the first input and the second input includes mapping i and j such that the i th bit and the j th bit are differently combined for respective instances of the operation.

11. The method of claim 10 , wherein the positive determination is based on when the operation value of the operation may be influenced by the operation being performed on, as an input, at least one of the operation values produced by a preceding instance of the operation, and the negative determination is based on when the operation output of the operation may not be influenced by the operation value produced by the preceding instance of the operation.

12. The method of claim 11 , further comprising:

skipping the operation based on the negative determination, and

determining an addition value and a carry value that are to be obtained based on the positive determination.

13. The method of claim 10 , wherein the determination of the positive determination or the negative determination is based on,

receiving at least one of a predetermined initial value, an operation value produced at a previous point of time, an operation value produced at a current point of time, an addition value produced by at the previous point of time, and/or a carry value produced at the previous point of time;

performing the positive determination based on the received values being the same as a first value; and

performing the negative determination when any one of the received values is the same as a second value.

14. The method of claim 10 , wherein the producing of one of the bits of the operation value of the operation includes performing the operation on, as inputs, a predetermined initial value, an operation value produced at a previous point of time, an operation value produced at a current point of time, an addition value produced at the previous point of time, and a carry value produced at the previous point of time.

15. The method of claim 10 , wherein at least one of an addition value or a carry value corresponds to a bit value of one of bits of the operation value of the operation.

16. The method of claim 10 , wherein the producing of one of the bits of the operation value of the operation includes, when a bit value of one of the bits of the operation value of the operation is produced, performing the operation again to produce another bit of the operation value of the operation.

17. The method of claim 10 , wherein the mapping of i and j comprises choosing i and j such that combinations, ranging from a combination of the i th bit and the j th bit such that a sum of i and j is smallest to a combination of the i th bit and the j th bit such that a sum of i and j is largest, are sequentially performed.

18. A non-transitory computer-readable recording medium having recorded thereon a program that, when executed by a computer, performs the method of claim 10 .