Ultra-dense ferroelectric memory with self-aligned patterning
Described is an ultra-dense ferroelectric memory. The memory is fabricated using a patterning method by that applies atomic layer deposition with selective dry and/or wet etch to increase memory density at a given via opening. A ferroelectric capacitor in one example comprises: a first structure (e.g., first electrode) comprising metal; a second structure (e.g., a second electrode) comprising metal; and a third structure comprising ferroelectric material, wherein the third structure is between and adjacent to the first and second structures, wherein a portion of the third structure is interdigitated with the first and second structures to increase surface area of the third structure. The increased surface area allows for higher memory density.
1. An apparatus comprising:
a dielectric layer over an interconnect, the dielectric layer comprising an opening, the opening defined by a sidewall of the dielectric layer and a portion of a barrier layer over the interconnect within the opening;
a first electrode structure comprising metal, the first electrode structure within the opening and conformal to the sidewall of the dielectric layer and the barrier layer within the opening;
a second electrode structure comprising metal, the second electrode structure comprising a pillar on the first electrode structure and within the opening;
a third structure comprising ferroelectric material on and conformal to surfaces of the first and second electrode structures; and
a third electrode structure comprising metal, the third electrode structure on the third structure, wherein the third structure is between the third electrode structure and the surfaces of the first and second electrode structures, and wherein a portion of the third electrode structure is interdigitated with the first and second electrode structures.
2. The apparatus of claim 1 , wherein the barrier layer comprises Ta, N, Ru, 1 r, Cu, Ru, or Mo.
3. The apparatus of claim 1 , further comprising a second barrier layer on the third electrode structure, and a second interconnect on the second barrier layer.
4. The apparatus of claim 1 , wherein the ferroelectric material comprises Hf or Zr.
5. The apparatus of claim 1 , wherein the ferroelectric material comprises Pb, Ti, Zr, Ba, N Si, La, Al, or Hf.
6. An apparatus comprising:
a bit-line;
a word-line;
a transistor coupled to the bit-line and the word-line; and
a capacitor over the bit-line (COB), wherein the COB is coupled to ground and the transistor, wherein the COB comprises:
a dielectric layer over an interconnect, the dielectric layer comprising an opening, the opening defined by a sidewall of the dielectric layer and a portion of a barrier layer over the interconnect within the opening;
a first electrode structure comprising metal, the first electrode structure within the opening and conformal to the sidewall of the dielectric layer and the barrier layer within the opening;
a second electrode structure comprising metal, the second electrode structure comprising a pillar on the first electrode structure and within the opening;
a third structure comprising ferroelectric material on and conformal to surfaces of the first and second electrode structures; and
a third electrode structure comprising metal, the third electrode structure on the third structure, wherein the third structure is between the third electrode structure and the surfaces of the first and second electrode structures, and wherein a portion of the third electrode structure is interdigitated with the first and second electrode structures.
7. The apparatus of claim 6 , wherein the barrier layer structure comprises Ta and N.
8. The apparatus of claim 7 , further comprising a second barrier layer on the third electrode structure, and a second interconnect on the second barrier layer.
9. The apparatus of claim 8 , wherein a sidewall of the second interconnect is aligned with the sidewall of the dielectric layer.
10. The apparatus of claim 9 , further comprising a second dielectric layer adjacent to the second sidewall of the second interconnect.
11. The apparatus of claim 8 , wherein the first and second interconnects comprise Cu, Al, graphene, carbon nanotubes, Co, Ti, or N.
12. The apparatus of claim 6 , wherein the ferroelectric material comprises Hf or Zr.
13. The apparatus of claim 6 , wherein the ferroelectric material comprises Pb, Ti, Zr, Ba, N, Si, La, Al, or Hf.
14. A system comprising:
a processor;
a memory coupled to the processor, wherein the memory comprises a capacitor comprising:
a dielectric layer over an interconnect, the dielectric layer comprising an opening, the opening defined by a sidewall of the dielectric layer and a portion of a barrier layer over the interconnect within the opening;
a first electrode structure comprising metal, the first electrode structure within the opening and conformal to the sidewall of the dielectric layer and the barrier layer within the opening;
a second electrode structure comprising metal, the second electrode structure comprising a pillar on the first electrode structure and within the opening;
a third structure comprising ferroelectric material on and conformal to surfaces of the first and second electrode structures; and
a third electrode structure comprising metal, the third electrode structure on the third structure, wherein the third structure is between the third electrode structure and the surfaces of the first and second electrode structures, and wherein a portion of the third electrode structure is interdigitated with the first and second electrode structures; and
a wireless interface to allow the processor to communicate with another device.
15. The system of claim 14 , wherein the first, second, and third electrode structures comprise Cu, Al, graphene, carbon nanotubes, Co, Ti, or N.
16. The system of claim 14 , wherein the ferroelectric material comprises O and Hf or Zr.
17. The system of claim 14 , wherein the memory comprises an embedded dynamic access memory, and wherein the capacitor is coupled to a transistor.
18. The system of claim 14 , wherein the capacitor is over a bit-line.
19. The system of claim 14 , wherein the capacitor is positioned in a backend of a die.
20. The system of claim 14 , further comprising:
a second barrier layer on the third electrode structure, wherein the barrier layer and the second barrier layer comprises Ta and N; and
a second interconnect on the second barrier layer, wherein the interconnect and the second interconnect comprise Cu, Al, graphene, carbon nanotubes, Co, Ti, or N.