IP Library › Granted Patent US 11,532,641
Granted Patent B2
US 11,532,641 · App. 17/027,390 · Granted Dec 20, 2022

Semiconductor device with ferroelectricity

Inventor: In Ku Kang (Icheon-si Gyeonggi-do, KR)
Assignee: SK hynix Inc.
H01L27/11597G11C15/04G11C15/046H01L27/11563H01L27/11585H01L27/11587
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Quick Facts
Patent No.
US 11,532,641
App. No.
17/027,390
Granted
Dec 20, 2022
Kind
B2
Abstract

A semiconductor device includes: a stack structure including conductive patterns and insulating layers, which are alternately stacked; a channel structure penetrating the stack structure; and a memory layer penetrating the stack structure, the memory layer being disposed between the channel structure and the stack structure. The memory layer includes memory parts and dummy parts, which are alternately arranged. Each of the memory parts includes a first part between the insulating layers and a second part between the dummy parts. The first part of the memory parts have ferroelectricity.

Claims (36)

1. A semiconductor device comprising:

a stack structure including conductive patterns and insulating layers, which are alternately stacked;

a channel structure penetrating the stack structure; and

a memory layer penetrating the stack structure, the memory layer being disposed between the channel structure and the stack structure,

wherein the memory layer includes memory parts and dummy parts, which are alternately arranged,

wherein each of the memory parts includes a first part between the insulating layers and a second part between the dummy parts, and

wherein the first part of each of the memory parts is spaced apart from the dummy parts and has ferroelectricity.

2. The semiconductor device of claim 1 ,

wherein the second part of each of the memory parts and the dummy parts have ferroelectricity, and

wherein a maximum residual polarization intensity of the memory parts is greater than that of the dummy parts.

3. The semiconductor device of claim 2 , wherein a volume ratio of single crystals having a crystal structure of an orthorhombic system at each of the memory parts is greater than that of single crystals having the crystal structure of the orthorhombic system at each of the dummy parts.

4. The semiconductor device of claim 2 , wherein the memory parts and the dummy parts have the same composition.

5. The semiconductor device of claim 2 , wherein an absolute value of a coercive electric field of the memory parts is greater than that of a coercive electric field of the dummy parts.

6. The semiconductor device of claim 1 , wherein the channel structure includes protrusion parts protruding toward the conductive patterns.

7. The semiconductor device of claim 6 , wherein the protrusion parts are disposed between the dummy parts.

8. The semiconductor device of claim 7 , wherein the dummy parts have paraelectricity.

9. The semiconductor device of claim 2 , wherein central levels of one of the conductive patterns and one of the memory parts, which are adjacent to each other, are substantially the same.

10. A semiconductor device comprising:

a stack structure including conductive patterns and insulating layers, which are alternately stacked;

a channel structure penetrating the stack structure; and

a memory layer penetrating the stack structure, the memory layer being disposed between the channel structure and the stack structure,

wherein the memory layer includes memory parts and dummy parts, which are alternately arranged,

wherein each of the memory parts includes a first part between the insulating layers and a second part between the dummy parts,

wherein the dummy parts are disposed between the insulating layers and the channel structure and in contact with the insulating layers, and

wherein the memory parts have ferroelectricity and

the dummy parts have paraelectricity.

11. The semiconductor device of claim 10 , wherein the first part is in contact with a top surface of one of the insulating layers and a bottom surface of another one of the insulating layers.

12. The semiconductor device of claim 10 , wherein the channel structure includes protrusion parts protruding toward the conductive patterns.

13. The semiconductor device of claim 12 , wherein the protrusion parts are disposed between the dummy parts.

14. The semiconductor device of claim 12 ,

wherein a central level of each of the dummy parts is substantially equal to that of each of the insulating layers, and

wherein a central level of each of the protrusion parts is substantially equal to that of each of the conductive patterns.

15. The semiconductor device of claim 10 , further comprising a filling layer penetrating the stack structure, the filling layer being disposed in the channel structure,

wherein a shortest distance between the conductive patterns and the filling layer is greater than that between the insulating layers and the filling layer.

16. The semiconductor device of claim 10 , further comprising an interposing layer between the memory layer and the stack structure.

17. The semiconductor device of claim 16 , wherein the interposing layer includes at least one of silicon oxide and hafnium oxide.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 21, 2020
From: KANG, IN KU
To: SK HYNIX INC.
Reel/Frame 053835/0237 →
Priority Claims (1)
KR 10-2020-0050932 · Apr 27, 2020 · national
Continuity (1)
Related Publication 20210335820A1 · Oct 28, 2021