Thin film transistor, display panel having the same, and method of manufacturing the display panel
A display panel includes a base layer, a first thin film transistor on the base layer, a second thin film transistor electrically coupled to the first thin film transistor, and a light emitting element electrically coupled to the second thin film transistor. The first thin film transistor includes a first semiconductor pattern on the base layer, a first barrier pattern on the first semiconductor pattern and including a gallium (Ga) oxide and a zinc (Zn) oxide, and a first control electrode on the first barrier pattern and overlapping the first semiconductor pattern. Accordingly, a signal transmission speed of the display panel may be improved, and electrical characteristics and reliability of the thin film transistor included in the display panel may be improved.
1. A display panel comprising:
a base layer;
a first thin film transistor on the base layer;
a second thin film transistor electrically coupled to the first thin film transistor; and
a light emitting element electrically coupled to the second thin film transistor, the first thin film transistor comprising:
a first semiconductor pattern on the base layer;
a first insulating layer on the base layer to cover the first semiconductor pattern;
a first barrier pattern directly on the first insulating layer and comprising a gallium (Ga) oxide and a zinc (Zn) oxide, wherein the first barrier pattern does not include indium (In); and
a first control electrode directly on the first barrier pattern and overlapping the first semiconductor pattern,
wherein a content of the gallium oxide is from about 4 at % to about 8 at % with respect to a total amount of atoms in the first barrier pattern, and a content of the zinc oxide is from about 92 at % to about 96 at % with respect to the total amount of atoms in the first barrier pattern.
2. The display panel of claim 1 , wherein the first thin film transistor comprises a first input electrode and a first output electrode, which are coupled to the first semiconductor pattern.
3. The display panel of claim 1 , wherein the first insulating layer is in contact with the first semiconductor pattern.
4. The display panel of claim 1 , further comprising a second insulating layer on the first insulating layer to cover the first control electrode, wherein the second thin film transistor comprises:
a second semiconductor pattern on the base layer;
a second barrier pattern on the second insulating layer and comprising the gallium (Ga) oxide and the zinc (Zn) oxide;
a second control electrode on the second barrier pattern and overlapping the second semiconductor pattern; and
a second input electrode and a second output electrode, which are coupled to the second semiconductor pattern.
5. The display panel of claim 4 , further comprising:
a third barrier pattern on the first insulating layer; and
a gate line on the third barrier pattern and electrically coupled to the first thin film transistor.
6. The display panel of claim 5 , further comprising a capacitor electrically coupled to the second thin film transistor, wherein the capacitor comprises:
a fourth barrier pattern on the first insulating layer;
a first electrode on the fourth barrier pattern;
a fifth barrier pattern on the second insulating layer; and
a second electrode on the fifth barrier pattern.
7. The display panel of claim 6 , wherein the third barrier pattern, the fourth barrier pattern, and the fifth barrier pattern comprise a same material as the first barrier pattern.
8. The display panel of claim 1 , wherein the first control electrode comprises:
a first layer comprising titanium (Ti); and
a second layer on the first layer and comprising copper (Cu).
9. The display panel of claim 1 , wherein the first semiconductor pattern comprises a gallium (Ga) oxide, a zinc (Zn) oxide, and an indium (In) oxide.
10. The display panel of claim 1 , wherein the first barrier pattern has a thickness equal to or greater than about 100 angstroms and equal to or smaller than about 200 angstroms.
11. The display panel of claim 1 , wherein the first insulating layer extends from the first thin film transistor to the second thin film transistor.