Source/drain isolation structures for leakage prevention
View Patent ↗The present disclosure is directed to gate-all-around (GAA) transistor structures with a low level of leakage current and low power consumption. For example, the GAA transistor includes a semiconductor layer with a first source/drain (S/D) epitaxial structure and a second S/D epitaxial structure disposed thereon, where the first and second S/D epitaxial structures are spaced apart by semiconductor nano-sheet layers. The semiconductor structure further includes isolation structures interposed between the semiconductor layer and each of the first and second S/D epitaxial structures. The GAA transistor further includes a gate stack surrounding the semiconductor nano-sheet layers.
1. A semiconductor structure, comprising:
a semiconductor layer;
a first source/drain (S/D) epitaxial structure and a second S/D epitaxial structure disposed on the semiconductor layer, wherein the first and second S/D epitaxial structures are spaced apart by semiconductor nano-sheet layers;
isolation structures interposed between the semiconductor layer and each of the first and second S/D epitaxial structures, wherein a thickness of a first one of the isolation structures extending from the first S/D epitaxial structure to the semiconductor layer is greater than a thickness of a second one of the isolation structures extending from the second S/D epitaxial structure to the semiconductor layer; and
a gate stack surrounding the semiconductor nano-sheet layers.
2. The semiconductor structure of claim 1 , wherein the isolation structures have a thickness between about 10 nm and about 200 nm.
3. The semiconductor structure of claim 1 , wherein the isolation structures have a rectangular shape.
4. The semiconductor structure of claim 1 , wherein the isolation structures extend laterally below the semiconductor nano-sheet layers by an amount between about 1 nm and about 3 nm.
5. The semiconductor structure of claim 1 , wherein the isolation structures are formed in a top portion of the semiconductor layer.
6. The semiconductor structure of claim 1 , wherein the isolation structures are formed on a top surface of the semiconductor layer.
7. The semiconductor structure of claim 1 , wherein the semiconductor layer is a top layer of a semiconductor-on-insulator (SOI) substrate.
8. The semiconductor structure of claim 1 , wherein the semiconductor layer is a top portion of a bulk wafer.
9. The semiconductor structure of claim 1 , wherein the semiconductor nano-sheet layers are vertically spaced apart by the gate stack in a middle portion of the semiconductor nano-sheet layers and by spacer structures in an edge portion of the semiconductor nano-sheet layers.
10. A semiconductor structure, comprising:
a substrate;
an oxide layer disposed on the substrate;
a semiconductor layer disposed on the oxide layer, wherein the semiconductor layer comprises a raised portion;
an isolation layer disposed on the semiconductor layer, wherein a sidewall of the raised portion abuts with a sidewall of the isolation layer;
a source/drain (S/D) region disposed on the isolation layer, wherein the isolation layer is configured to electrically isolate the S/D region from the semiconductor layer and wherein a width of the isolation layer is greater than a width of the S/D region;
nano-sheet layers disposed on the semiconductor layer;
a spacer structure disposed adjacent to the S/D region, wherein an interface between the spacer structure and the S/D region is misaligned with an interface between the raised portion and the isolation layer; and
a gate structure surrounding the nano-sheet layers.
11. The semiconductor structure of claim 10 , wherein the semiconductor layer comprises an undoped semiconductor material.
12. The semiconductor structure of claim 10 , wherein the semiconductor layer comprises a doped semiconductor material.
13. The semiconductor structure of claim 10 , wherein the isolation layer comprises an oxide material or a nitride material.
14. The semiconductor structure of claim 10 , wherein the isolation layer comprises an oxide of a material of the semiconductor layer.
15. The semiconductor structure of claim 10 , wherein the isolation layer comprises an electrical resistivity greater than about 1×10 10 Ohms·m.
16. A semiconductor structure, comprising:
a substrate comprising a first portion and a second portion, wherein the first portion extends vertically above the second portion;
nano-sheet layers disposed on the substrate;
a gate structure surrounding a middle portion of the nano-sheet layers and disposed on and in physical contact with the first portion of the substrate;
spacers surrounding edge portions of the nano-sheet layers uncovered by the gate structure;
an isolation layer disposed on a second portion of the substrate uncovered by the gate structure, wherein the isolation layer extends laterally under the spacers; and
a source/drain (S/D) epitaxial region disposed on the isolation layer, wherein the edge portions of the nano-sheet layers are in contact with the S/D epitaxial region, and wherein an interface between the S/D region and one of the spacers is misaligned with an interface between a sidewall of the first portion and a sidewall of the isolation layer.
17. The semiconductor structure of claim 16 , wherein the isolation layer extends laterally below the nano-sheet layers.
18. The semiconductor structure of claim 16 , wherein the isolation layer is in contact with one of the spacers.
19. The semiconductor structure of claim 16 , wherein the isolation layer comprises at least a 10 nm thick oxide or nitride material with an electrical resistivity greater than about 1×10 10 Ohms·m.
20. The semiconductor structure of claim 16 , wherein the substrate comprises an undoped semiconductor material.