Semiconductor device including oxide semiconductor layer
Aspects of the present inventive concept provide a semiconductor device capable of enhancing performance and reliability through source/drain engineering in a transistor including an oxide semiconductor layer. The semiconductor device includes a substrate, a metal oxide layer disposed on the substrate, a source/drain pattern being in contact with the metal oxide layer and including a portion protruding from a top surface of the metal oxide layer, a plurality of gate structures disposed on the metal oxide layer with the source/drain pattern interposed therebetween and each including gate spacers and an insulating material layer, the insulating material layer being in contact with the metal oxide layer, and not extending along a top surface of the source/drain pattern, and a contact disposed on the source/drain pattern, the contact being connected to the source/drain pattern.
1. A semiconductor device comprising:
a substrate;
a metal oxide layer disposed on the substrate;
a source/drain pattern being in contact with the metal oxide layer and including a portion protruding from a top surface of the metal oxide layer;
a plurality of gate structures disposed on the metal oxide layer with the source/drain pattern interposed therebetween, and each of the gate structures including gate spacers and an insulating material layer, the insulating material layer being in contact with the metal oxide layer, and not extending along a top surface of the source/drain pattern; and
a contact disposed on the source/drain pattern, the contact being connected to the source/drain pattern,
wherein the source/drain pattern is in contact with the gate spacers,
the insulating material layer is in direct contact with the gate spacers and does not overlap the gate spacers in a direction perpendicular to a top surface of the substrate,
the gate spacers define a gate trench, and
the insulating material layer extends along sidewalls and a bottom surface of the gate trench.
2. The semiconductor device of claim 1 , wherein the source/drain pattern includes sidewall portions extending along sidewalls of the gate structures and a bottom portion extending along the top surface of the substrate.
3. The semiconductor device of claim 1 , wherein the source/drain pattern includes a lower source/drain pattern and an upper source/drain pattern on the lower source/drain pattern, and
the lower source/drain pattern and the upper source/drain pattern have at least one of different materials and different shapes from each other.
4. The semiconductor device of claim 1 , wherein the metal oxide layer includes a source/drain recess formed between two adjacent ones of the gate structures, and
a portion of the source/drain pattern fills the source/drain recess.
5. The semiconductor device of claim 1 , wherein the source/drain pattern includes at least one of silicon (Si), silicon germanium (SiGe), silicon carbide (SiC), germanium (Ge), indium tin oxide (ITO), indium zinc oxide (IZO) and InGaSiO.
6. The semiconductor device of claim 5 , wherein the source/drain pattern includes a dopant, and
the dopant includes at least one of phosphorus (P), arsenic (As), antimony (Sb) and boron (B).
7. The semiconductor device of claim 1 , wherein the insulating material layer includes a first paraelectric material layer and a ferroelectric material layer sequentially stacked on the metal oxide layer.
8. The semiconductor device of claim 1 , further comprising a source/drain pattern liner formed on the source/drain pattern, the source/drain pattern liner extending along an adjacent one of the gate spacers and disposed between the adjacent one of the gate spacers and the contact,
wherein the source/drain pattern liner includes an insulating material.
9. The semiconductor device of claim 8 , wherein the source/drain pattern liner includes an etch stop liner and a hydrogen diffusion prevention liner.
10. The semiconductor device of claim 1 , further comprising a buried liner layer disposed between the metal oxide layer and the substrate, the buried liner layer being in contact with the metal oxide layer and including a transition metal.
11. The semiconductor device of claim 1 , wherein the metal oxide layer includes one of amorphous metal oxide, polycrystalline metal oxide and a combination thereof.
12. A semiconductor device comprising:
a substrate;
a metal oxide layer disposed on the substrate;
a plurality of gate structures spaced apart from each other and disposed on the metal oxide layer;
a source/drain pattern disposed between the gate structures, the source/drain pattern being connected to the metal oxide layer and including at least one of an element semiconductor material pattern and a group Iv-Iv compound semiconductor material pattern; and
a contact disposed on the source/drain pattern, the contact being connected to the source/drain pattern,
wherein each of the gate structures includes gate spacers defining a gate trench and an insulating material layer extending along sidewalls and a bottom surface of the gate trench.
13. The semiconductor device of claim 12 , wherein the source/drain pattern includes a dopant, and
the dopant includes at least one of phosphorus (P), arsenic (As), antimony (Sb) and boron (B).
14. The semiconductor device of claim 12 , wherein the source/drain pattern further includes a conductive oxide pattern, and
the conductive oxide pattern includes at least one of indium tin oxide (ITO), indium zinc oxide (IZO) and InGaSiO.
15. The semiconductor device of claim 14 , wherein the conductive oxide pattern includes sidewall portions extending along sidewalls of the gate structures and a bottom portion extending along a top surface of the substrate.
16. The semiconductor device of claim 12 , wherein each of the gate structures includes a paraelectric material layer and a ferroelectric material layer sequentially stacked on the metal oxide layer.
17. A semiconductor device comprising:
a silicon substrate;
a buffer insulating layer disposed on the silicon substrate, the buffer insulating layer extending along a top surface of the silicon substrate;
a metal oxide layer disposed on the buffer insulating layer, the metal oxide layer including In—Ga—Zn-based oxide;
a plurality of gate structures spaced apart from each other, each of the gate structures including a gate electrode and a capping pattern on the gate electrode;
a source/drain pattern disposed between the gate structures, the source/drain pattern being in contact with the metal oxide layer and including sidewall portions extending along sidewalls of the gate structures and a bottom portion extending along the top surface of the silicon substrate;
an interlayer insulating layer covering the source/drain pattern and the gate structures and including a contact hole exposing at least a portion of the source/drain pattern; and
a contact filling the contact hole and connected to the source/drain pattern,
wherein each of the gate structures includes gate spacers defining a gate trench and an insulating material layer extending along sidewalls and a bottom surface of the gate trench.
18. The semiconductor device of claim 17 , wherein the source/drain pattern includes at least one of indium tin oxide (ITO), indium zinc oxide (IZO) and InGaSiO.
19. The semiconductor device of claim 17 , wherein the metal oxide layer includes a source/drain recess formed between two adjacent ones of the gate structures, and
a portion of the source/drain pattern fills the source/drain recess.