Sense amplifying circuit of semiconductor memory device for offset cancellation operation

1. A semiconductor memory device, comprising:

a bit line sense amplifier coupled between a pull-up voltage line and a pull-down voltage line, and suitable for sensing a voltage difference between first and second bit lines by sequentially performing a precharge operation, an offset cancellation operation, a charge sharing operation, and an amplification operation, wherein the bit line sense amplifier pre-biases a voltage level of the second bit line depending on a voltage level of the first bit line during the charge sharing operation; and

a driving circuit suitable for supplying operating voltages to the pull-up voltage line and the pull-down voltage line during the offset cancellation operation, the charge sharing operation, and the amplification operation,

wherein the charge sharing operation includes a main charge sharing operation and a pre-biasing operation, which are sequentially performed, and

wherein, during the pre-biasing operation, the bit line sense amplifier biases the voltage level of the second bit line depending on the voltage level of the first bit line and the driving circuit provides the operating voltage to the pull-up voltage line and the pull-down voltage line.

2. The semiconductor memory device of claim 1 , wherein, during the main charge sharing operation, the bit line sense amplifier operates to isolate the first bit line from the second bit line, and the driving circuit stops supplying the operating voltage to the pull-up voltage line and the pull-down voltage line.

3. The semiconductor memory device of claim 1 , further comprising a precharge circuit suitable for supplying a precharge voltage to the pull-up voltage line, the pull-down voltage line, and the first and second bit lines during the precharge operation.

4. A sense amplifying circuit, comprising:

a first inverter having an input terminal coupled to a first bit line and an output terminal coupled to a second inner bit line;

a second inverter having an input terminal coupled to a second bit line and an output terminal coupled to a first inner bit line;

a first offset cancellation switch suitable for electrically coupling the first inner bit line to the second bit line during an offset cancellation operation;

a second offset cancellation switch suitable for electrically coupling the second inner bit line to the first bit line during the offset cancellation operation;

a first isolation switch suitable for electrically coupling the first inner bit line to the first bit line during an amplification operation; and

a second isolation switch suitable for electrically coupling the second inner bit line to the second bit line during a charge sharing operation and the amplification operation, wherein the charge sharing operation includes a main charge sharing operation and a pre-biasing operation, and the first isolation switch is turned off and the second isolation switch is turned on, during the pre-biasing operation.

5. The sense amplifying circuit of claim 4 , wherein the sense amplifying circuit sequentially performs a precharge operation, the offset cancellation operation, the charge sharing operation, and the amplification operation.

6. The sense amplifying circuit of claim 5 , wherein the first and second inner bit lines and the first and second bit lines are precharged to a same voltage level during the precharge operation.

7. The sense amplifying circuit of claim 5 , wherein the first and second inverters are deactivated and the first and second offset cancellation switches and the first and second isolation switches are turned on, during the precharge operation.

8. The sense amplifying circuit of claim 4 , wherein the first and second inverters are activated and the first and second offset cancellation switches are turned on and the first and second isolation switches are turned off, during the offset cancellation operation.

9. The sense amplifying circuit of claim 4 ,

wherein the first and second offset cancellation switches and the first and second isolation switches are turned off during the main charge sharing operation, and

wherein the first and second offset cancellation switches and the first isolation switch are turned off and the second isolation switch is turned on, during the pre-biasing operation.

10. The sense amplifying circuit of claim 4 , wherein the first and second inverters are activated and the first and second offset cancellation switches are turned off and the first and second isolation switches are turned on, during the amplification operation.

11. A sense amplifying circuit, comprising:

a pull-up circuit including first and second pull-up transistors respectively coupled between a pull-up voltage line and first and second inner bit lines, the first and second pull-up transistors having a cross-coupled structure;

a pull-down circuit including first and second pull-down transistors respectively coupled between a pull-down voltage line and the first and second inner bit lines;

a first offset cancellation switch suitable for electrically coupling the first inner bit line to a second bit line during an offset cancellation operation;

a second offset cancellation switch suitable for electrically coupling the second inner bit line to a first bit line during the offset cancellation operation;

a first isolation switch suitable for electrically coupling the first inner bit line to the first bit line during an amplification operation;

a second isolation switch suitable for electrically coupling the second inner bit line to the second bit line during the amplification operation;

a first pre-biasing switch suitable for electrically coupling a gate of the second pull-down transistor to the first bit line during the offset cancellation operation, a charge sharing operation and the amplification operation; and

a second pre-biasing switch suitable for electrically coupling a gate of the first pull-down transistor to the second bit line during the offset cancellation operation and the amplification operation.

12. The sense amplifying circuit of claim 11 , wherein the sense amplifying circuit sequentially performs a precharge operation, the offset cancellation operation, the charge sharing operation, and the amplification operation.

13. The sense amplifying circuit of claim 12 , wherein the first and second inner bit lines and the first and second bit lines are precharged to a same voltage level during the precharge operation.

14. The sense amplifying circuit of claim 12 , wherein the first and second offset cancellation switches, the first and second isolation switches, and the first and second pre-biasing switches are turned on during the precharge operation.

15. The sense amplifying circuit of claim 11 , wherein the first and second offset cancellation switches and first and second pre-biasing switches are turned on and the first and second isolation switches are turned off, during the offset cancellation operation.

16. The sense amplifying circuit of claim 11 ,

wherein the charge sharing operation includes a main charge sharing operation and a pre-biasing operation,

wherein the first and second offset cancellation switches and the first and second isolation switches, and the first and second pre-biasing switches are turned off during the main charge sharing operation, and

wherein the first and second offset cancellation switches and the second pre-biasing switch are turned off and the first and second isolation switches and the first pre-biasing switch are turned on, during the pre-biasing operation.

17. The sense amplifying circuit of claim 11 , wherein the first and second offset cancellation switches are turned off and the first and second isolation switches and the first and second pre-biasing switches are turned on, during the amplification operation.

18. An operating method of a semiconductor memory device, the operating method comprising performing:

a precharge operation of precharging target and reference bit lines to a precharge level;

a charge sharing operation of making the target bit line share a charge stored in a target memory cell for the target bit line to have a voltage level different from the reference bit line;

a pre-biasing operation of adjusting the voltage level of the reference bit line to an inverted voltage level of the target bit line; and

an amplification operation of amplifying a voltage difference between the target and reference bit lines.