Semiconductor device
A semiconductor package including a semiconductor chip, a redistribution layer structure disposed under the semiconductor chip, a bump pad disposed under the redistribution layer structure and having an upper structure of a first width and a lower structure of a second width less than the first width, a metal seed layer disposed along a lower surface of the upper structure and a side surface of the lower structure, an insulating layer surrounding the redistribution layer structure and the bump pad, and a bump structure disposed under the bump pad. A first undercut is disposed at one end of the metal seed layer that contacts the upper structure, and a second undercut is disposed at an other end of the metal seed layer that contacts the lower structure.
1. A semiconductor package comprising:
a semiconductor chip;
a redistribution layer structure disposed under the semiconductor chip;
a bump pad disposed under the redistribution layer structure, the bump pad having an upper structure of a first width and a lower structure of a second width less than the first width;
a metal seed layer disposed along a lower surface of the upper structure and a side surface of the lower structure;
an insulating layer surrounding the redistribution layer structure and the bump pad; and
a bump structure disposed under the bump pad,
wherein a first undercut is disposed at one end of the metal seed layer that contacts the upper structure, and a second undercut is disposed at an other end of the metal seed layer that contacts the lower structure.
2. The semiconductor package of claim 1 , wherein the redistribution layer structure comprises:
a plurality of redistribution layer lines; and
a plurality of vias connected to the plurality of redistribution layer lines,
wherein the plurality of vias have a tapered shape that narrows away from the semiconductor chip.
3. The semiconductor package of claim 1 , wherein the first undercut and the second undercut extend orthogonal to each other.
4. The semiconductor package of claim 3 , wherein the first undercut is filled with the insulating layer, and the second undercut is filled with the bump structure.
5. The semiconductor package of claim 4 , wherein the bump structure has a third width greater than the second width of the lower structure.
6. The semiconductor package of claim 3 , wherein the first undercut is filled with the insulating layer, and the second undercut is empty.
7. The semiconductor package of claim 6 , wherein the bump structure has a third width, and the second width of the lower structure is greater than or equal to the third width of the bump structure.
8. The semiconductor package of claim 1 , wherein the metal seed layer comprises at least one of titanium (Ti), titanium tungsten (TiW), and chromium (Cr).
9. The semiconductor package of claim 1 , wherein a level of a lower surface of the lower structure and a level of a lowest surface of the insulating layer are the same,
wherein the bump structure is in contact with the lower surface and the side surface of the lower structure, and
wherein the bump structure is in contact with a side surface of the insulating layer, and is not in contact with the lower surface of the insulating layer.
10. The semiconductor package of claim 1 , wherein an upper surface of the upper structure is upwardly convex or downwardly concave.
11. A semiconductor package comprising:
a first sub-package including a first semiconductor chip;
a second sub-package disposed on the first sub-package and including a second semiconductor chip; and
an inter-package connection structure connecting the first sub-package to the second sub-package,
wherein each of the first sub-package and the second sub-package comprises
a lower redistribution layer structure,
a bump pad disposed under the lower redistribution layer structure, the bump pad having an upper structure of a first width and a lower structure of a second width less than the first width,
a metal seed layer disposed along a lower surface of the upper structure and a side surface of the lower structure,
a lower insulating layer surrounding the lower redistribution layer structure and the bump pad, and
a bump structure disposed under the bump pad,
wherein a first undercut is disposed at one end of the metal seed layer that contacts the upper structure and a second undercut is disposed at an other end of the metal seed layer that contacts the lower structure.
12. The semiconductor package of claim 11 , wherein the first sub-package further comprises a frame structure disposed around a side surface of the first semiconductor chip, and
wherein the frame structure and the lower redistribution layer structure of the first sub-package are electrically connected to each other by a through electrode disposed inside the frame structure.
13. The semiconductor package of claim 12 , wherein the inter-package connection structure connects the frame structure of the first sub-package to the lower redistribution layer structure of the second sub-package.
14. The semiconductor package of claim 11 , wherein the first undercut and the second undercut extend orthogonal to each other.
15. The semiconductor package of claim 14 , wherein the bump structure has a third width greater than the second width of the lower structure,
wherein the first undercut is filled with the lower insulating layer, and
wherein the second undercut is filled with the bump structure.
16. The semiconductor package of claim 14 , wherein the bump structure has a third width, and the second width of the lower structure is greater than or equal to the third width of the bump structure,
wherein the first undercut is filled with the lower insulating layer, and
wherein the second undercut is empty.
17. The semiconductor package of claim 11 , wherein a level of a lower surface of the lower structure and a level of a lowest surface of the lower insulating layer are the same,
wherein the bump structure is in contact with the lower surface and the side surface of the lower structure, and
wherein the bump structure is in contact with a side surface of the lower insulating layer, and is not in contact with the lower surface of the insulating layer.
18. A semiconductor package comprising:
a bump structure;
a T-shaped bump pad disposed on the bump structure, the T-shaped bump pad having an upper structure and a lower structure with a step difference between the upper structure and the lower structure;
a redistribution layer structure disposed on the T-shaped bump pad and having a plurality of redistribution layer lines;
a plurality of insulating layers surrounding the redistribution layer structure and the T-shaped bump pad;
a metal seed layer conformally disposed between a lower surface of the upper structure and a lowermost insulating layer of the plurality of insulating layers, and between a side surface of the lower structure and the lowermost insulating layer; and
a semiconductor chip disposed on the redistribution layer structure and electrically connected to the bump structure,
wherein a first undercut is disposed at one end of the metal seed layer, a second undercut is disposed at an other end of the metal seed layer, and the first undercut and the second undercut extend orthogonal to each other.
19. The semiconductor package of claim 18 , further comprising:
additional semiconductor chips disposed on the redistribution layer structure; and
a molding member surrounding the semiconductor chip and the additional semiconductor chips.
20. The semiconductor package of claim 18 , wherein a thickness of the metal seed layer between the T-shaped bump pad and the lowermost insulating layer is about 100 Å to about 20,000 Å, and
wherein the metal seed layer comprises at least one of titanium (Ti), titanium tungsten (TiW), and chromium (Cr).