IP Library › Granted Patent US 11,538,926
Granted Patent B2
US 11,538,926 · App. 16/837,908 · Granted Dec 27, 2022

Semiconductor device and method of manufacturing a semiconductor device

Inventors: Yu-Cheng Shen (Hsinchu, TW); Guan-Jie Shen (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
H01L29/66795H01L21/02183H01L21/02186H01L21/02194H01L21/823431H01L29/785
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,538,926
App. No.
16/837,908
Granted
Dec 27, 2022
Kind
B2
Abstract

A method of manufacturing a semiconductor device includes forming a plurality of work function metal layers and an oxygen absorbing layer over a channel region of the semiconductor device, including forming a first work function metal layer over the channel region, forming an oxygen absorbing layer over the first work function metal layer, forming a second work function metal layer over the oxygen absorbing layer. A gate electrode metal layer is formed over the plurality of work function metal layers. The work function metal layers, oxygen absorbing layer, and gate electrode metal layer are made of different materials.

Claims (47)

1. A method of manufacturing a semiconductor device, comprising:

forming a plurality of work function metal layers and an oxygen absorbing layer over a channel region of the semiconductor device, comprising:

forming a first work function metal layer over the channel region;

forming an oxygen absorbing layer over the first work function metal layer; and

forming a second work function metal layer over the oxygen absorbing layer;

forming a gate electrode metal layer over the plurality of work function metal layers,

wherein the work function metal layers, oxygen absorbing layer, and gate electrode metal layer are made of different materials; and

forming a gate dielectric layer over the channel region; and

forming another oxygen absorbing layer over the gate dielectric layer before forming the plurality of work function metal layers over the channel region of the semiconductor device.

2. The method according to claim 1 , wherein the oxygen absorbing layer is made of one or more selected from the group consisting of Al, Y, Mg, Ti, Ta, and Si.

3. The method according to claim 1 , wherein the plurality of work function metal layers include a first type work function metal layer and a second type work function metal layer, and the first type work function metal layer and the second type work function metal layer are made of different materials.

4. The method according to claim 3 , wherein the first type work function metal layer is a p-type work function metal layer and the second type work function metal layer is an n-type work function metal layer.

5. The method according to claim 3 , wherein the first type work function metal layer is made of one or more selected from the group consisting of TaN, TiN, TaSiN, WN, TiC, WCN, MoN, and Co.

6. The method according claim 3 , wherein the second type work function metal layer is made of one or more selected from the group consisting of TiAl, TiAlC, TiAlN, TaAl, and TaAlC.

7. The method according to claim 3 , wherein:

the forming a plurality of work function layers includes forming a plurality of the first type work function metal layers; and

wherein the forming an oxygen absorbing layer includes forming an oxygen absorbing layer between each of the first type work function metal layers.

8. The method according to claim 3 , wherein:

the forming a plurality of work function layers includes forming a plurality of the second type work function metal layers; and

wherein the forming an oxygen absorbing layer includes forming an oxygen absorbing layer between each of the second type work function metal layers.

9. A method of manufacturing a semiconductor device, comprising:

forming a plurality of first metal nitride layers and a second metal nitride layer over a channel region of the semiconductor device, wherein the first metal nitride layers and the second metal nitride layer comprise a first metal, comprising:

forming a first first metal nitride layer over the channel region;

forming the second metal nitride layer over the first first metal nitride layer; and

forming a second first metal nitride layer over the second metal nitride layer; and

forming a gate electrode metal layer over the plurality of first metal nitride layers,

wherein the second metal nitride layer has a greater concentration of the first metal than the first metal nitride layer, and

the first and second metal nitride layers, and the gate electrode metal layer are formed of different materials.

10. The method according to claim 9 , wherein the first metal nitride layers are thicker than the second metal nitride layers.

11. The method according to claim 9 , wherein the first and second metal nitride layers are formed by a material deposition operation, and the second metal nitride layer is formed by changing one or more deposition parameters used to form the first metal nitride layers.

12. The method according to claim 11 , where the deposition parameters are one or more selected from the group consisting of concentration of metal nitride reactants, pressure, feed rate of the metal nitride reactants, and time duration of supplying the metal nitride reactants.

13. The method according to claim 9 , further comprising forming a metal layer comprising a second metal over the first and second metal nitride layers, wherein the second metal is different from the first metal.

14. The method according to claim 13 , further comprising forming additional first and second metal nitride layers over the metal layer comprising the second metal before forming the gate metal electrode layer.

15. A semiconductor device, comprising:

a gate stack structure disposed over a channel region of semiconductor substrate,

wherein the gate stack structure comprises:

a gate dielectric layer disposed over the channel region;

a first oxygen absorbing layer disposed over the gate dielectric layer;

a plurality of work function metal layers disposed over the first oxygen absorbing layer;

a second oxygen absorbing layer disposed between a pair of the work function metal layers; and

a gate electrode metal layer disposed over the plurality of work function metal layers,

wherein the work function metal layers, oxygen absorbing layers, and gate electrode metal layer are different materials.

16. The semiconductor device of claim 15 , wherein the gate stack structure is formed over a fin structure protruding from the semiconductor substrate.

17. The semiconductor device of claim 15 , wherein the oxygen absorbing layer comprises one or more selected from the group consisting of Al, Y, Mg, Ti, Ta, and Si.

18. The semiconductor device of claim 15 , wherein the plurality of work function metal layers include a first work function metal layer and a second work function metal layer, and the first work function metal layer and the second work function metal layer are made of different materials.

19. The semiconductor device of claim 18 , further comprising an oxygen absorbing layer between each of the first type work function metal layers.

20. The method according to claim 18 , further comprising an oxygen absorbing layer between each of the second type work function metal layers.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2020
From: SHEN, YU-CHENG; SHEN, GUAN-JIE
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 052415/0245 →
Continuity (1)
Related Publication 20210313454A1 · Oct 7, 2021