Nanostructures and method for manufacturing the same

1. A method, comprising:

forming a stack of a first type and a second type epitaxial layers on a frontside of a semiconductor substrate, the first type and second type epitaxial layers having different material compositions, the first type and second type epitaxial layers being alternatingly disposed in a vertical direction;

patterning the stack to form a fin-shaped structure;

depositing a dielectric layer on sidewalls of the fin-shaped structure;

recessing the dielectric layer to expose a top portion of the fin-shaped structure, wherein a top surface of the recessed dielectric layer is above a bottom surface of the stack;

forming a gate structure over the top portion of the fin-shaped structure;

etching the semiconductor substrate from a backside of the semiconductor substrate, thereby forming a trench between the dielectric layer, the trench exposing the bottom surface of the stack; and

etching at least a bottommost first type epitaxial layer and a bottommost second type epitaxial layer through the trench.

2. The method of claim 1 , wherein the bottommost first type epitaxial layer is under the bottommost second type epitaxial layer, and wherein the top surface of the recessed dielectric layer is above a top surface of the bottommost first type epitaxial layer.

3. The method of claim 2 , wherein the top surface of the recessed dielectric layer is below a top surface of the bottommost second type epitaxial layer.

4. The method of claim 1 , wherein the gate structure is a metal gate structure, and wherein the etching of at least the bottommost first type epitaxial layer and the bottommost second type epitaxial layer is after the forming of the gate structure.

5. The method of claim 1 , further comprising:

prior to the forming of the gate structure, removing the first type epitaxial layers from the top portion of the fin-shaped structure,

wherein after the forming of the gate structure, the gate structure wraps around the second type epitaxial layers in the top portion of the fin-shaped structure.

6. The method of claim 1 , wherein after the forming of the gate structure, the bottommost second type epitaxial layer has a top surface interfacing with the gate structure and a bottom surface interfacing with the bottommost first type epitaxial layer.

7. The method of claim 1 , wherein the etching of at least the bottommost first type epitaxial layer and the bottommost second type epitaxial layer includes fully removing the bottommost first type epitaxial layer and partially removing the bottommost second type epitaxial layer from the trench.

8. The method of claim 1 , wherein the etching of at least the bottommost first type epitaxial layer and the bottommost second type epitaxial layer includes etching multiple second type epitaxial layers.

9. The method of claim 1 , further comprising:

depositing a dielectric material in the trench, wherein a portion of the bottommost second type epitaxial layer protrudes into the dielectric material.

10. A method, comprising:

forming a first plurality of channel members over a first region of a substrate, the first plurality of channel members being vertically stacked;

forming a second plurality of channel members over a second region of a substrate, the second plurality of channel members being vertically stacked;

forming an isolation feature in the first and second regions, wherein a top surface of the isolation feature is higher in the second region than in the first region, such that a portion of the second plurality of channel members is below the top surface of the isolation feature in the second region;

forming a first gate structure engaging the first plurality of channel members, thereby forming a first transistor in the first region;

forming a second gate structure engaging the second plurality of channel members, thereby forming a second transistor in the second region; and

removing the portion of the second plurality of channel members from the second region, such that a number of the first plurality of channel members in the first transistor is larger than a number of the second plurality of channel members in the second transistor.

11. The method of claim 10 , wherein the forming of the isolation feature includes:

depositing a dielectric material over sidewalls of the first and second pluralities of channel members;

recessing the dielectric material in the first and second regions, thereby exposing a top portion of the first and second pluralities of channel members; and

further recessing the dielectric material in the first region, such that the first plurality of channel members are fully above the dielectric material.

12. The method of claim 10 , further comprising:

etching the substrate in the first and second regions, thereby forming trenches in the first and second regions, wherein the removing of the portion of the second plurality of channel members exposes the second gate structure in the trenches in the second region.

13. The method of claim 12 , wherein the etching of the substrate exposes the first gate structure in the trenches in the first region.

14. The method of claim 10 , further comprising:

forming first source/drain features abutting the first plurality of channel members; and

forming second source/drain features abutting the second plurality of channel members, wherein a thickness of the second source/drain features is smaller than a thickness of the first source/drain features.

15. The method of claim 14 , further comprising:

forming first inner spacer features interposing the first source/drain features and the first gate structure;

forming second inner spacer features interposing the second source/drain features and the second gate structure; and

recessing the second source/drain features, such that a bottommost second inner spacer feature is spaced apart from the second source/drain features.

16. The method of claim 10 , wherein the first gate structure wraps around each of the first plurality of channel members in the first region and the second gate structure wraps around each of a top portion of the second plurality of channel members in the second region.

17. A semiconductor device, comprising:

a first gate structure engaging a first plurality of channel members;

a second gate structure engaging a second plurality of channel members;

a first backside dielectric feature disposed directly under the first gate structure; and

a second backside dielectric feature disposed directly under the second gate structure,

wherein a number of the first plurality of channel members is larger than a number of the second plurality of channel members.

18. The semiconductor device of claim 17 , wherein a height of the first gate structure is larger than a height of the second gate structure.

19. The semiconductor device of claim 17 , wherein a thickness of the first backside dielectric feature is smaller than a thickness of the second backside dielectric feature.

20. The semiconductor device of claim 17 , further comprising:

first inner spacer features abutting the first gate structure; and

second inner spacer features abutting the second gate structure, wherein a bottom portion of the second inner spacer features extends into the second backside dielectric feature.