IP Library › Granted Patent US 11,544,061
Granted Patent B2
US 11,544,061 · App. 17/131,034 · Granted Jan 3, 2023

Analog hardware matrix computation

Inventors: Malte Johannes Rasch (Chappaqua, NY); Oguzhan Murat Onen (Boston, MA); Tayfun Gokmen (Briarcliff Manor, NY); Chai Wah Wu (Hopewell Junction, NY); Mark S. Squillante (Greenwich, CT); Tomasz J. Nowicki (Fort Montgomery, NY); Wilfried Haensch (Somers, NY); Lior Horesh (North Salem, NY); Vasileios Kalantzis (White Plains, NY); Haim Avron (Tel-Aviv, IL)
Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION; RAMOT AT TEL AVIV UNIVERSITY LTD.
G06F9/30036G06F9/3001G06F9/5011
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Quick Facts
Patent No.
US 11,544,061
App. No.
17/131,034
Granted
Jan 3, 2023
Kind
B2
Abstract

Methods and systems for solving a linear system include setting resistances in an array of settable electrical resistances in accordance with values of an input matrix. A series of input vectors is applied to the array as voltages to generate a series of respective output vectors. Each input vector in the series of vectors is updated based on comparison of the respective output vectors to a target vector. A solution of a linear system is determined that includes the input matrix based on the updated input vectors.

Claims (30)

1. A method for solving a linear system, comprising:

setting resistances in a hardware array of settable electrical resistance devices in accordance with values of an input matrix;

applying a series of input vectors to the array as voltages to generate a series of respective output vectors as currents, including integrating output currents of the array over time;

updating each input vector in the series of vectors based on comparison of the respective output vectors to a target vector; and

determining a solution of a linear system that includes the input matrix based on the updated input vectors.

2. The method of claim 1 , wherein updating each input vector includes iteratively updating each input vector until the input vectors respectively converge.

3. The method of claim 2 , wherein convergence is determined responsive to a difference between successive updated input vectors being below a threshold value.

4. The method of claim 2 , wherein updating each input vector is performed as a stochastic gradient descent.

5. The method of claim 1 , wherein setting the resistances comprises determining an array matrix A based on the input matrix Ã, where A=Ã{circumflex over ( )}T Ã.

6. The method of claim 1 , wherein setting the resistances comprises applying first voltages on input lines of the array and applying second voltages on output lines of the array, such that voltages that add to a total voltage at a settable electrical resistance that is above a threshold change the resistance value of the settable electrical resistance.

7. The method of claim 1 , wherein the solution of the linear system includes an inverse of the input matrix.

8. The method of claim 7 , wherein the series of input vectors includes n input vectors, and wherein the target vector is a corresponding column of the identity matrix.

9. The method of claim 1 , wherein updating each input vector is based on a difference between the respective output vector and the target vector.

10. A non-transitory computer readable storage medium comprising a computer readable program for solving a linear system, wherein the computer readable program when executed on a computer causes the computer to:

set resistances in a hardware array of settable electrical resistance devices in accordance with values of an input matrix;

apply a series of input vectors to the array as voltages to generate a series of respective output vectors as currents, including integrating output currents of the array over time;

update each input vector in the series of vectors based on comparison of the respective output vectors to a target vector; and

determine a solution of a linear system that includes the input matrix based on the updated input vectors.

11. A system for solving a linear system, comprising:

a hardware array of settable electrical resistance devices that includes a set of output lines, each having a respective integrator that integrates output currents over time;

a hardware processor; and

a memory that stores computer program code which, when executed by the hardware processor, implements:

a solver that sets resistances in the array of settable electrical resistance devices in accordance with values of an input matrix, applies a series of input vectors to the array as voltages to generate a series of respective output vectors as currents based on the integrated output currents, updates each input vector in the series of vectors based on comparison of the respective output vectors to a target vector, and determines a solution of a linear system that includes the input matrix based on the updated input vectors.

12. The system of claim 11 , wherein the solver iteratively updates each input vector until the input vectors respectively converge.

13. The system of claim 12 , wherein convergence is determined responsive to a difference between successive updated input vectors being below a threshold value.

14. The system of claim 12 , wherein the solver updates each input vector with a stochastic gradient descent.

15. The system of claim 11 , wherein the solver applies first voltages on input lines of the array and applying second voltages on output lines of the array to set the resistances, such that voltages that add to a total voltage at a settable electrical resistance that is above a threshold change the resistance value of the settable electrical resistance.

16. The system of claim 11 , wherein the solution of the linear system includes an inverse of the input matrix.

17. The system of claim 16 , wherein the series of input vectors includes a input vectors, and wherein the target vector is a corresponding column of the identity matrix.

18. The system of claim 11 , wherein the solver updates each input vector based on a difference between the respective output vector and the target vector.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 22, 2020
From: RASCH, MALTE JOHANNES; ONEN, OGUZHAN MURAT; GOKMEN, TAYFUN; WU, CHAI WAH; SQUILLANTE, MARK S.; NOWICKI, TOMASZ J.; HAENSCH, WILFRIED; HORESH, LIOR; KALANTZIS, VASILEIOS
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 054730/0910 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 22, 2020
From: AVRON, HAIM
To: RAMOT AT TEL AVIV UNIVERSITY LTD.
Reel/Frame 054731/0024 →
Continuity (1)
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