IP Library › Granted Patent US 11,544,168
Granted Patent B2
US 11,544,168 · App. 16/858,455 · Granted Jan 3, 2023

Memory system

Inventors: Wan-Jun Roh (Goyang, KR); Hyung-Sup Kim (Yongin, KR); Hyung-Sik Won (Cheongju, KR)
Assignee: SK hynix Inc.
G06F11/3037G06F11/3058G06F12/0877G11C5/141G11C11/4074G11C11/40607G11C11/40626
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Quick Facts
Patent No.
US 11,544,168
App. No.
16/858,455
Granted
Jan 3, 2023
Kind
B2
Abstract

A memory system may improve the endurance and performance of a plurality of memories included in the memory system mounted on a server system or a data processing system. For example, the memory system may throttle energy of a first memory using a second memory having a different characteristic from the first memory, control accesses to a memory region according to a refresh cycle, and control accesses to memories having different temperatures according to a priority of a request for each of the memories.

Claims (10)

1. A memory system, comprising:

a first memory group including a cache region;

a second memory group having a different characteristic from the first memory group, the second memory group being physically separated from the first memory group; and

a controller including a first interface for interfacing with the first memory group and a second interface for interfacing with the second memory group,

wherein the controller is configured to store hot data of the second memory group into the cache region, and when a temperature or an energy consumption of a memory included in the second memory group is equal to or higher than a threshold value, throttle the memory by buffering data in the cache region in response to a write request for the memory, and

wherein the controller migrates the hot data of the second memory group into the cache region of the first memory group through the second interface and the first interface.

2. The memory system of claim 1 , wherein the controller disables the cache region when a temperature or an energy consumption of the cache region is equal to or higher than the threshold value.

3. The memory system of claim 1 , wherein the first memory group is a volatile memory group, and the second memory group is a non-volatile memory group.

4. The memory system of claim 3 , further comprising a supercapacitor configured to supply a back-up power to the memory system, and

wherein, when a power supply of the memory system is cut off, the controller flushes data stored in the cache region into the non-volatile memory group using the back-up power.

Priority Claims (3)
KR 10-2017-0142584 · Oct 30, 2017 · national
KR 10-2017-0153774 · Nov 17, 2017 · national
KR 10-2018-0019212 · Feb 19, 2018 · national
Continuity (4)
Continuation In Part 16164411 · Oct 18, 2018
Continuation In Part 16159479 · Oct 12, 2018
Continuation In Part 16136069 · Sep 19, 2018
Related Publication 20200257604A1 · Aug 13, 2020