Semiconductor storage device, memory system, and method
A semiconductor storage device includes a bridge chip and memory chips connected to the bridge chip by a plurality of channels. The bridge chip includes a first delay circuit for setting the start of a first timing signal for a first memory chip output via a first channel and a second delay circuit for setting the start of for second timing signal for a second memory chip output via a second channel. A controller on the bridge chip controls at least one of the first and second delay circuits to adjust the start time of at least one of the first and second timing signals such that data sequences from the first and second memory chips will be aligned in time. The controller combines the data sequence from the first memory chip with the data sequence from the second memory chip to generate an interleaved serial sequence.
1. A semiconductor storage device, comprising:
a bridge chip with an external terminal group configured to be connected to a host; and
a plurality of memory chips including a first memory chip connected to the bridge chip by a first channel and a second memory chip connected to the bridge chip by a second channel, wherein
the bridge chip comprises:
a first delay circuit configured to set a transmission start timing for a first timing signal output to the first memory chip via the first channel, the first timing signal initiating transmission of a data sequence from the first memory chip via the first channel;
a second delay circuit configured to set a transmission start timing for a second timing signal output to the second memory chip via the second channel, the second timing signal initiating transmission of a data sequence from the second memory chip via the second channel; and
a controller configured to:
control at least one of the first and second delay circuits to adjust the transmission start timing of at least one of the first and second timing signals such that the data sequence from the first memory chip and the data sequence from the second memory chip will be aligned in time, and
combine the data sequence from the first memory chip and the data sequence from the second memory chip into an interleaved serial sequence.
2. The semiconductor storage device according to claim 1 , wherein the controller is configured to:
measure a read enable latency for each of the first memory chip and the second memory chip,
store the measured read enable latency for each of the first memory chip and the second memory chip, and
control the first and second delay circuits to set the transmission start timings for the first and second timing signals according to the stored read enable latency for each of the first memory chip and the second memory chip.
3. The semiconductor storage device according to claim 2 , wherein the controller is further configured to measure the read enable latency for each of the first memory chip and the second memory chip in response to an instruction from the host.
4. The semiconductor storage device according to claim 1 , wherein the plurality of memory chips includes a plurality of first memory chips connected to the bridge chip by the first channel and a plurality of second memory chips connected to the bridge chip by the second channel.
5. The semiconductor storage device according to claim 4 , wherein the controller is configured to:
measure a read enable latency for each of the first memory chips and each of the second memory chips,
store the measured read enable latency for each of the first memory chips and each of the second memory chips, and
control the first and second delay circuits to set the transmission start timings for the first and second timing signals according to at least the stored read enable latency for a targeted one of the first memory chips and a targeted one of the second memory chips.
6. The semiconductor storage device according to claim 5 , wherein the controller is further configured to measure the read enable latency for each of the first memory chips and the second memory chips in response to an instruction from the host.
7. The semiconductor storage device according to claim 5 , wherein the controller is further configured to:
calculate a difference between the measured values of the read enable latency for a targeted first memory chip in the plurality of first memory chips and a targeted second memory chip in the plurality of second memory chips,
set the calculated difference as a delay time for the transmission start timing for the first or second timing signal, and
set a delay time for the transmission start timing for the other of the first or second timing signal to zero.
8. The semiconductor storage device according to claim 1 , wherein the controller is configured to:
measure a read enable latency for the first memory chip and a read enable latency for the second memory chip,
calculate a difference between the measured values of the read enable latency for the first memory chip and the second memory chip,
set the calculated difference as a delay time for the transmission start timing for the first or second timing signal, and
set a delay time for the transmission start timing for the other of the first or second timing signal to zero.
9. The semiconductor storage device according to claim 1 , wherein the interleaved serial sequence is transmitted to the host via a third channel at a frequency that is at least twice a frequency of the transmission of the data sequence from the first memory chip via the first channel.
10. The semiconductor storage device according to claim 1 , wherein the controller is configured to transmit, in response to a data output command from the host, a read enable signal to the first memory chip via the first delay circuit in parallel with a read enable signal to the second memory chip via the second delay circuit.
11. A memory system, comprising:
a host device; and
a semiconductor storage device connected to the host device by a host channel, the semiconductor storage device including:
a bridge chip with an external terminal group connected to the host channel; and
a plurality of memory chips including a first memory chip connected to the bridge chip by a first channel and a second memory chip connected to the bridge chip by a second channel, wherein
the bridge chip comprises:
a first delay circuit configured to set a transmission start timing for a first timing signal output to the first memory chip via the first channel, the first timing signal initiating transmission of a data sequence from the first memory chip via the first channel;
a second delay circuit configured to set a transmission start timing for a second timing signal output to the second memory chip via the second channel, the second timing signal initiating transmission of a data sequence from the second memory chip via the second channel; and
a controller configured to:
control at least one of the first and second delay circuits to adjust the transmission start timing of at least one of the first and second timing signals such that the data sequence from the first memory chip and the data sequence from the second memory chip will be aligned in time,
combine the data sequence from the first memory chip and the data sequence from the second memory chip into an interleaved serial sequence, and
transmit the interleaved serial sequence to the host device via the host channel.
12. The memory system according to claim 11 , wherein the controller is configured to:
measure a read enable latency for each of the first memory chip and the second memory chip,
store the measured read enable latency for each of the first memory chip and the second memory chip, and
control the first and second delay circuits to set the transmission start timings for the first and second timing signals according to the stored read enable latency for each of the first memory chip and the second memory chip.
13. The memory system according to claim 12 , wherein the controller is further configured to measure the read enable latency for each of the first memory chip and the second memory chip in response to an instruction from the host device.
14. The memory system according to claim 11 , wherein the plurality of memory chips includes a plurality of first memory chips connected to the bridge chip by the first channel and a plurality of second memory chips connected to the bridge chip by the second channel.
15. The memory system according to claim 14 , wherein the controller is configured to:
measure a read enable latency for each of the first memory chips and each of the second memory chips,
store the measured read enable latency for each of the first memory chips and each of the second memory chips, and
control the first and second delay circuits to set the transmission start timings for the first and second timing signals according to at least the stored read enable latency for a targeted one of the first memory chips and a targeted one of the second memory chips.
16. The memory system according to claim 15 , wherein the controller is further configured to measure the read enable latency for each of the first memory chips and the second memory chips in response to an instruction from the host device.
17. The memory system according to claim 11 , wherein the interleaved serial sequence is transmitted to the host device via the host channel at a frequency that is at least twice a frequency of the transmission of the data sequence from the first memory chip via the first channel.
18. The memory system according to claim 11 , wherein the controller is configured to transmit, in response to a data output command from the host device, a read enable signal to the first memory chip via the first delay circuit in parallel with a read enable signal to the second memory chip via the second delay circuit.
19. A method for controlling parallel read operations of a semiconductor storage device including a plurality of memory chips connected to a bridge chip by a plurality of channels, the method comprising:
setting a transmission start timing for a first timing signal output to a first memory chip via a first channel based on a read enable latency for the first memory chip, the first timing signal initiating transmission of a data sequence from the first memory chip via the first channel; and
setting a transmission start timing for a second timing signal output to a second memory chip via a second channel based on a read enable latency for the second memory chip, the second timing signal initiating transmission of a data sequence from the second memory chip via the second channel, wherein
at least one of the first and second timing signals is set such that the data sequence from the first memory chip and the data sequence from the second memory chip will be aligned in time.
20. The method according to claim 19 , further comprising:
combining the data sequence from the first memory chip and the data sequence from the second memory chip into an interleaved serial sequence; and
transmitting the interleaved serial sequence to a host device via a third channel.