Gaming super resolution

1. A processing device comprising:

memory; and

a processor configured to:

receive an input image having a first resolution;

generate at least one linear down-sampled version of the input image via a linear upscaling network;

generate at least one non-linear down-sampled version of the input image via a non-linear upscaling network;

convert the at least one linear down-sampled version of the input image and the at least one non-linear down-sampled version of the input image into pixels of an output image having a second resolution higher than the first resolution by assigning a co-located pixel in each of the down-sampled versions of the input image to each of a plurality of pixel blocks of the output image, wherein different pixel positions of the plurality of pixel blocks comprise the co-located pixel from a corresponding down-sampled version of the input image; and

provide the output image for display.

2. The processing device of claim 1 , wherein the processor is configured to generate the at least one non-linear down-sampled version of the input image, via the non-linear upscaling network, by stacking an activation function between each of a plurality of convolutional operations to convert a series of linear operations into a series of non-linear operations.

3. The processing device of claim 1 , wherein the processor is configured to generate the at least one linear down-sampled version of the input image, via the linear upscaling network, by performing one or more convolution operations on a window of pixels of the input image.

4. The processing device of claim 1 , wherein the processor is configured to convert the at least one linear down-sampled version of the input image and the at least one non-linear down-sampled version of the input image into pixels by generating, for the output image, the plurality of pixel blocks, each pixel block comprising the co-located pixel from each of the down-sampled versions of the input image.

5. The processing device of claim 1 , wherein a total number of the different pixel positions of each pixel block is equal to a total number of the down-sampled versions of the input image.

6. The processing device of claim 1 , wherein the linear upscaling network comprises one or more convolution operations, the non-linear upscaling network comprises a plurality of convolution operations, each convolution operation produces a same number of linear down-sampled versions or a same number of non-linear down-sampled versions each time a corresponding convolution operation is performed.

7. A processing device comprising:

memory; and

a processor configured to:

receive an input image having a first resolution;

generate a plurality of non-linear down-sampled versions of the input image via a non-linear upscaling network;

generate a plurality of linear down-sampled versions of the input image via a linear upscaling network;

combine the plurality of non-linear down-sampled versions and the plurality of linear down-sampled versions to provide a plurality of combined down-sampled versions of the input image;

convert the combined down-sampled versions of the input image into pixels of an output image having a second resolution higher than the first resolution by assigning, to each of a plurality of pixel blocks of the output image, a co-located pixel in each of the combined down-sampled versions; and

provide the output image for display.

8. The processing device of claim 7 , wherein each of the plurality of non-linear down-sampled versions comprises at least one of color features, non-color features and features which have color information and non-color information.

9. The processing device of claim 7 , wherein the processor is configured to generate the plurality of non-linear down-sampled versions of the input image in parallel with the plurality of linear down-sampled versions of the input image.

10. The processing device of claim 7 , wherein the processor is configured to generate the plurality of non-linear down-sampled versions by stacking activation functions between convolutional operations to convert a series of linear operations into a series of non-linear operations.

11. The processing device of claim 7 , wherein the processor is configured to generate the plurality of linear down-sampled versions of the input image, via the linear upscaling network, by performing at least one convolution operation on a window of pixels of the input image.

12. The processing device of claim 7 , wherein each pixel block of the output image comprises a plurality of pixels, each pixel located at one of a number of different positions of each pixel block, and

each position comprises the co-located pixel from a corresponding down-sampled version of the input image.

13. The processing device of claim 12 , wherein a total number of the different pixel positions of each pixel block is equal to a total number of the down-sampled versions of the input image.

14. The processing device of claim 7 , wherein the linear upscaling network comprises one or more convolution operations, the non-linear upscaling network comprises a plurality of convolution operations, each convolution operation produces a same number of linear down-sampled versions or a same number of non-linear down-sampled versions each time a corresponding convolution operation is performed.

15. A super resolution processing method comprising:

receiving an input image having a first resolution;

generating at least one linear down-sampled version of the input image via a linear upscaling network;

generating at least one non-linear down-sampled version of the input image via a non-linear upscaling network;

converting the at least one linear down-sampled version of the input image and the at least one non-linear down-sampled version of the input image into pixels of an output image having a second resolution higher than the first resolution by assigning a co-located pixel in each of the down-sampled versions of the input image to each of a plurality of pixel blocks of the output image, wherein different pixel positions of the plurality of pixel blocks comprise the co-located pixel from a corresponding down-sampled version of the input image; and

providing the output image for display.

16. The method of claim 15 , wherein generating the at least one non-linear down-sampled version of the input image, via the non-linear upscaling network, comprises stacking an activation function between each of a plurality of convolutional operations to convert a series of linear operations into a series of non-linear operations.

17. The method of claim 15 , wherein generating the at least one linear down-sampled version of the input image, via the linear upscaling network, comprises performing a convolution operation on a window of pixels of the input image.

18. The method of claim 15 , wherein converting the at least one linear down-sampled version of the input image and the at least one non-linear down-sampled version of the input image into pixels by generating, for the output image, the plurality of pixel blocks, each pixel block comprising the co-located pixel from each of the down-sampled versions of the input image.

19. The method of claim 15 , wherein the linear upscaling network comprises one or more convolution operations, the non-linear upscaling network comprises a plurality of convolution operations, each convolution operation produces a same number of linear down-sampled versions or a same number of non-linear down-sampled versions each time a corresponding convolution operation is performed.