Apparatus, memory device, and method for storing multiple parameter codes for operation parameters
Provided are an apparatus, a memory device, and a method for storing a plurality of parameter codes for an operation parameter. The memory device includes a mode register and a control logic circuit. To set a first operating condition and a second operating condition for one operation parameter, the mode register stores a first parameter code for the operation parameter and a second parameter code, which is expressed as an offset value from the first parameter code. The control logic circuit sets the first operating condition as a current operating condition of the memory device by using the first parameter code based on a first control code and sets the second operating condition as the current operating condition of the memory device by using the first parameter code and the second parameter code based on a second control code.
1. An apparatus comprising:
a plurality of signal pins connected to a plurality of signal lines, wherein each signal pin of the plurality of signal pins is connected to a signal line of the plurality of signal lines, and each signal line carries a signal; and
a mode register set configured to store a first parameter code and a second parameter code for one operation parameter of the apparatus in a first register and a second register, respectively,
wherein the first parameter code comprises a global operation parameter code associated with an operating condition for signal pins associated with the one operation parameter,
the second parameter code comprises a per-pin operation parameter code associated with operating conditions of the respective signal pins associated with the one operation parameter, and
the per-pin operation parameter code is expressed as an offset value from the global operation parameter code.
2. The apparatus of claim 1 , wherein, to set a current operating condition for the one operation parameter, the mode register set is further configured to store a first control code for selecting the first parameter code in a third register and store a second control code for selecting the second parameter code in a fourth register.
3. The apparatus of claim 1 , wherein the one operation parameter comprises a decision feedback equalizer (DFE) quantity operation parameter associated with operating conditions of data (DQ) pins, and
wherein the signal pins comprise the DQ pins.
4. The apparatus of claim 3 , wherein the first parameter code comprises a first global operation parameter code and a second global operation parameter code,
the first global operation parameter code is a lower byte DFE quantity parameter code for lower DQ byte pins from among the DQ pins, and
the second global operation parameter code is an upper byte DFE quantity parameter code for upper DQ byte pins from among the DQ pins.
5. The apparatus of claim 1 , further comprising a reference voltage generation circuit connected to the plurality of signal lines,
wherein the one operation parameter comprises a reference voltage operation parameter associated with the reference voltage generation circuit.
6. The apparatus of claim 1 , further comprising an on-die termination (ODT) circuit connected to the plurality of signal lines,
wherein the one operation parameter comprises an operation parameter associated with the ODT circuit.
7. The apparatus of claim 1 , wherein the one operation parameter comprises an operation parameter associated with command/address (CA) pins from among the signal pins.
8. The apparatus of claim 1 , wherein the one operation parameter comprises at least one of a swing width parameter, a driving strength parameter, a pre-emphasis parameter, an on-die termination (ODT) parameter, a reference voltage parameter, or a decision feedback equalizer (DFE) quantity parameter associated with the signal pins.
9. A memory device configured to be set to a current operating condition, the memory device comprising:
a mode register configured to store a first parameter code and a second parameter code for one operation parameter of the memory device to set a first operating condition and a second operating condition for the one operation parameter; and
a control logic circuit configured to set the first operating condition as the current operating condition by using the first parameter code for the one operation parameter based on a first control code stored in the mode register and to set the second operating condition as the current operating condition by using the first parameter code and the second parameter code for the one operation parameter based on a second control code stored in the mode register,
wherein the second parameter code is expressed as an offset value from the first parameter code.
10. The memory device of claim 9 , wherein the first parameter code comprises a global operation parameter code associated with the first operating condition, and the second parameter code comprises a per-pin operation parameter code associated with the second operating condition.
11. The memory device of claim 10 , wherein the first parameter code comprises a first global operation parameter code and a second global operation parameter code,
the first global operation parameter code is a lower byte operation parameter code for lower data (DQ) byte pins from among DQ pins of the memory device, and
the second global operation parameter code is an upper byte operation parameter code for upper DQ byte pins from among the DQ pins.
12. The memory device of claim 9 , further comprising a decision feedback equalizer (DFE) circuit,
wherein the one operation parameter comprises a DFE quantity parameter associated with the DFE circuit.
13. The memory device of claim 9 , further comprising a reference voltage generation circuit,
wherein the one operation parameter comprises a reference voltage operation parameter associated with the reference voltage generation circuit.
14. The memory device of claim 9 , further comprising an on-die termination (ODT) circuit,
wherein the one operation parameter comprises an operation parameter associated with the ODT circuit.
15. The memory device of claim 9 , wherein the one operation parameter comprises an operation parameter associated with command/address (CA) pins.
16. The memory device of claim 9 , wherein the memory device is configured to perform a training operation for determining the first parameter code and the second parameter code for the one operation parameter through a memory controller outside the memory device.
17. The memory device of claim 16 , wherein the first operating condition and the second operating condition are associated with an operating condition for a memory bus coupled between the memory device and the memory controller.
18. The memory device of claim 17 , wherein operation parameters associated with an operation parameter regarding the memory bus comprise at least one of a swing width parameter, a pre-emphasis parameter, an on-die termination (ODT) parameter, a reference voltage parameter, or a decision feedback equalizer (DFE) quantity parameter.
19. A method of setting a current operating condition of a memory device, the method comprising:
storing a first parameter code used to set a first operating condition for one operation parameter in a first register of a mode register;
storing a second parameter code used to set a second operating condition for the one operation parameter in a second register of the mode register, wherein the second parameter code is expressed as an offset value from the first parameter code;
setting the first operating condition as the current operating condition by using the first parameter code for the one operation parameter; and
setting the second operating condition as the current operating condition by using the first parameter code and the second parameter code for the one operation parameter.
20. The method of claim 19 , further comprising selecting the first parameter code or both the first parameter code and the second parameter code to set the current operating condition.