Semiconductor wafer, semiconductor chip, and dicing method
A semiconductor wafer according to the present embodiment is a semiconductor wafer having a first face. A plurality of chip structures are provided on a plurality of chip regions of the first face. A test structure is provided on dicing regions between adjacent ones of the chip regions. The chip structures each comprise first integrated circuits provided on the semiconductor wafer, and a first stacked body provided above the first integrated circuits and including a plurality of first layers and a plurality of second layers different from the first layers alternately stacked. The test structure comprises second integrated circuits provided on the semiconductor wafer, and a second stacked body provided above the second integrated circuits and including the first layers and the second layers alternately stacked.
1. A semiconductor wafer including a first face, the wafer comprising:
a plurality of chip structures provided on a plurality of chip regions of the first face; and
a test structure provided on dicing regions between adjacent ones of the chip regions, wherein
the chip structures each comprise a plurality of first transistors provided on the semiconductor wafer, and a first stacked body provided above the plurality of first transistors and including a plurality of first layers and a plurality of second layers different from the first layers alternately stacked,
a semiconductor body extending in a stacking direction of the first stacked body in the first stacked body,
a memory film comprising charge storing portions between the second layers and the semiconductor body, and
a first metal contact extending in a stacking direction of the first stacked body in the first stacked body and electrically connected to one of the plurality of first transistors,
wherein the test structure comprises a plurality of second transistors provided on the semiconductor wafer, and a second stacked body provided above the plurality of second transistors and including the first layers and the second layers alternately stacked, and
a second metal contact extending in a stacking direction of the second stacked body in the second stacked body and electrically connected to one of the plurality of second transistors.
2. The wafer according to claim 1 , further comprising a slit structure extending in a stacking direction of the second stacked body in the second stacked body.
3. The wafer according to claim 1 , wherein the second layers are made of a metallic material.
4. The water according to claim 1 , wherein the test structure further comprises a third stacked body provided on the plurality of second transistors and including the plurality of first layers and a plurality of third layers alternately stacked, the plurality of third layers being made of a material different from that of the first layers.
5. The wafer according to claim 4 , wherein
the first layers are silicon dioxide films, and
the third layers are silicon nitride films.
6. A semiconductor chip including a first face, the chip comprising:
a chip structure provided on the first face; and
a test structure provided on an outer edge portion of the semiconductor chip, wherein
the chip structure comprises a plurality of first transistors provided on the semiconductor wafer, and a first stacked body provided on the plurality of first transistors and including a plurality of first layers and a plurality of second layers alternately stacked,
a semiconductor body extending in a stacking direction of the first stacked body in the first stacked body,
a memory film comprising charge storing portions between the second layers and the semiconductor body, and
a first metal contact extending in a stacking direction of the first stacked body in the first stacked body and electrically connected to one of the plurality of first transistors,
wherein the test structure comprises a plurality of second transistors provided on the semiconductor wafer, and a second stacked body provided on the plurality of second transistors and including the first layers and the second layers alternately stacked, and
a second metal contact extending in a stacking direction of the second stacked body in the second stacked body and electrically connected to one of the plurality of second transistors.
7. The semiconductor chip according to claim 6 , further comprising a second contact extending in a stacking direction of the second stacked body in the second stacked body and electrically connected to any of the second transistors.
8. The semiconductor chip according to claim 6 , further comprising a slit structure extending in a stacking direction of the second stacked body in the second stacked body.
9. The semiconductor chip according to claim 6 , wherein the second layers are made of a metallic material.
10. The semiconductor chip according to claim 6 , wherein the test structure further comprises a third stacked body provided on the second transistors and including the first layers and a plurality of third layers alternately stacked, the third layers being made of a material different from that of the first layers.
11. The semiconductor chip according to claim 10 , wherein
the first layers are silicon dioxide films, and
the third layers are silicon nitride films.