Nanosheet (NS) and fin field-effect transistor (FinFET) hybrid integration
Certain aspects of the present disclosure are directed to a semiconductor device. The semiconductor device generally includes a substrate, at least one silicon-on-insulator (SOI) transistor disposed above the substrate, a gate-all-around (GAA) transistor disposed above the substrate, and a fin field-effect transistor (FinFET) disposed above the substrate.
1. A semiconductor device comprising:
a substrate;
at least one silicon-on-insulator (SOI) transistor disposed above the substrate;
a gate-all-around (GAA) transistor disposed above the substrate; and
a fin field-effect transistor (FinFET) disposed above the substrate.
2. The semiconductor device of claim 1 , wherein the at least one SOI transistor comprises:
a p-type metal-oxide-semiconductor (PMOS) transistor; and
an n-type metal-oxide-semiconductor (NMOS) transistor, the NMOS transistor and the PMOS transistor forming a complementary metal-oxide-semiconductor (CMOS) device.
3. The semiconductor device of claim 1 , wherein the GAA transistor comprises an n-type GAA transistor, and wherein the FinFET comprises a p-type FinFET.
4. The semiconductor device of claim 1 , wherein:
the substrate is a (100) crystal plane substrate;
a top surface of a channel of the at least one SOI transistor has a (100) orientation crystal plane;
a sidewall of a fin of the FinFET has a <110> orientation crystal plane; and
a top surface of a slab of the GAA transistor has a (100) orientation crystal plane.
5. The semiconductor device of claim 4 , wherein:
a sidewall of at least one gate region of the at least one SOI transistor has a <110> orientation crystal plane;
a sidewall of a gate region of the FinFET has a <110> orientation crystal plane; and
a sidewall of a gate region of the GAA transistor has a <110> orientation crystal plane.
6. The semiconductor device of claim 1 , wherein the at least one SOI transistor comprises:
a well region disposed above the substrate;
an oxide region disposed above the well region;
a channel region disposed above the oxide region;
a gate oxide disposed above the channel region; and
a gate region disposed above the gate oxide.
7. The semiconductor device of claim 1 , wherein the FinFET comprises:
a well region disposed above the substrate;
at least one fin disposed above the well region; and
a gate region disposed adjacent to the at least one fin.
8. The semiconductor device of claim 1 , wherein the GAA transistor comprises:
a well region disposed above the substrate;
one or more slabs disposed above the well region; and
a gate region disposed adjacent to the one or more slabs.
9. The semiconductor device of claim 8 , wherein the gate region is disposed around each of the one or more slabs.
10. The semiconductor device of claim 1 , further comprising:
a shallow trench isolation region disposed between the FinFET and the at least one SOI transistor.
11. The semiconductor device of claim 1 , wherein:
the SOI transistor is laterally spaced apart from the FinFET; and
the FinFET is laterally spaced apart from the GAA transistor.
12. The semiconductor device of claim 1 , wherein the SOI transistor, the FinFET, and the GAA transistor are collinear.
13. The semiconductor device of claim 1 , wherein:
the GAA transistor is a first distance from the SOI transistor;
the GAA transistor is a second distance from the FinFET; and
the first distance is greater than the second distance.
14. The semiconductor device of claim 1 , wherein a top of the SOI transistor, a top of the FinFET, and a top of the GAA transistor are substantially a same distance from the substrate.