IP Library › Granted Patent US 11,545,494
Granted Patent B2
US 11,545,494 · App. 17/075,849 · Granted Jan 3, 2023

Semiconductor device having low-k spacer and converting spacer and method for fabricating the same

Inventors: Yun-Hyuck Ji (Seoul, KR); Beom-Ho Mun (Gyeonggi-do, KR); In-Sang Kim (Gyeongsangnam-do, KR)
Assignee: SK hynix Inc.
H01L27/10888H01L21/02126H01L21/02129H01L21/02164H01L21/31144H01L21/3213H01L21/76826H01L21/76895
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Quick Facts
Patent No.
US 11,545,494
App. No.
17/075,849
Granted
Jan 3, 2023
Kind
B2
Abstract

A method for fabricating a semiconductor device includes forming a line structure including a first contact plug on a semiconductor substrate and a conductive line on the first contact plug, forming a low-k layer having a first low-k, which covers a top surface and side walls of the line structure, performing a converting process on the low-k layer to form a non-converting portion adjacent to side walls of the first contact plug and maintains the first low-k and a converting portion adjacent to side walls of the conductive line and having a second low-k that is lower than the first low-k, and forming a second contact plug which is adjacent to the first contact plug with the non-converting portion therebetween while being adjacent to the conductive line with the converting portion therebetween.

Claims (34)

1. A semiconductor device, comprising:

a conductive structure including a first contact plug and a conductive line on the first contact plug;

a second contact plug;

a first multi-layer spacer including a low-k spacer located between the first contact plug and the second contact plug; and

a second multi-layer spacer including a converting spacer located between the conductive line and the second contact plug,

wherein the converting spacer extended vertically from the low-k spacer to be located between the conductive line and the second contact plug,

wherein the converting spacer includes an oxide converted from the low-k spacer, and

wherein the low-k spacer occupies a maximum volume in the first multi-layer spacer, and the converting spacer occupies a maximum volume in the second multi-layer spacer.

2. The semiconductor device of claim 1 , wherein the low-k spacer includes a low-k material.

3. The semiconductor device of claim 1 , wherein the low-k spacer includes a low-k material, and the converting spacer includes a silicon oxide oxidized from the low-k material.

4. The semiconductor device of claim 1 , wherein the low-k spacer includes a silicon-based material including carbon, boron, or a combination thereof, and the converting spacer includes a silicon oxide oxidized from the silicon-based material.

5. The semiconductor device of claim 1 , wherein the low-k spacer includes at least one silicon-based material selected from SiCO, SiCN, SiOCN, SiBN and SiBCN, and the converting spacer includes a silicon oxide oxidized from the silicon-based material.

6. The semiconductor device of claim 1 , wherein the converting spacer has a line shape formed parallel to both side walls of the conductive line.

7. The semiconductor device of claim 1 , wherein the low-k spacer has a plug shape located on both side walls of the first contact plug.

8. The semiconductor device of claim 1 , wherein the first contact plug includes a bit line contact plug, the conductive line includes a bit line, and the second contact plug includes a storage node contact plug.

9. The semiconductor device of claim 1 , further comprising:

a semiconductor substrate including a first impurity region coupled to the first contact plug and a second impurity region coupled to the second contact plug; and

a dielectric material formed on the semiconductor substrate and including a first contact hole exposing the first impurity region,

wherein the first contact hole is filled with the first contact plug and the low-k spacer.

10. The semiconductor device of claim 9 , further comprising:

a gate trench between the first impurity region and the second impurity region;

a buried word line formed in the gate trench; and

a memory element formed on the second contact plug.

11. A semiconductor device comprising:

a conductive structure including a first contact plug and a conductive line on the first contact plug;

a second contact plug;

a low-k spacer located between the first contact plug and the second contact plug;

a converting spacer extended vertically from the low-k spacer to be located between the conductive line and the second contact plug, wherein the converting spacer includes an oxide converted from the low-k spacer;

a first silicon nitride spacer located between the converting spacer and the conductive line; and

a second silicon nitride spacer located between the converting spacer and the second contact plug,

wherein the first silicon nitride spacer is extended between the low-k spacer and the second contact plug.

12. The semiconductor device of claim 11 , wherein the first silicon nitride spacer and the second silicon nitride spacer are thinner than the low-k spacer and the converting spacer.

13. The semiconductor device of claim 11 , wherein the low-k spacer has an etch selectivity over the first and second silicon nitride spacers.

14. The semiconductor device of claim 11 , wherein the low-k spacer includes a silicon-based material containing an impurity including carbon, boron, or a combination thereof, and the first and second silicon nitride spacers include a silicon nitride containing no impurity.

Priority Claims (1)
KR 10-2018-0034450 · Mar 26, 2018 · national
Continuity (2)
Continuation 16193453 · Nov 16, 2018
Related Publication 20210035984A1 · Feb 4, 2021
Cited By (1)
US 12,672,278