Systems and methods for phase locked loop realignment with skew cancellation

1. A phase locked loop comprising:

a phase/frequency detector configured to receive a reference signal and a feedback signal;

a charge pump configured to receive first and second outputs from the phase/frequency detector and to generate pulses;

an oscillator configured to generate an output waveform based on the charge pump pulses;

a filter between the charge pump and the oscillator; and

a realignment path configured to generate a clock realignment signal that is provided to the oscillator based on a third output from the charge pump after the third output from the charge pump bypasses the filter and is routed through a third matching gate.

2. The loop of claim 1 , wherein the charge pump comprises a first matching gate and a second matching gate.

3. The loop of claim 2 , wherein the first, second, and third matching gates are all AND gates or are all OR gates.

4. The loop of claim 1 , wherein the filter is a low pass filter configured to receive the pulses from the charge pump and to generate an input to the oscillator.

5. The loop of claim 1 , wherein the clock realignment signal is periodically generated to reset any accumulated error in the phase locked loop.

6. The loop of claim 1 , wherein the realignment path receives no input from before the phase/frequency detector.

7. The loop of claim 1 , wherein the realignment path does not include a programmable delay line or a delay locked loop.

8. The loop of claim 1 , further comprising a feedback path that provides the output waveform to the phase/frequency detector as the feedback signal.

9. The loop of claim 8 , wherein the feedback path comprises a frequency divider.

10. The loop of claim 1 , wherein the reference signal is provided to the phase/frequency detector after a delay period, wherein the delay period is determined by an automated place and route routine of computer-aided circuit design software.

11. The loop of claim 10 , wherein the charge pump receives the first and second outputs from the phase/frequency detector after a second delay period, wherein the second delay period is user selectable using the computer-aided design software.

12. The loop of claim 1 , wherein the realignment path comprises a pulse generator, wherein the realignment signal is generated by the pulse generator, the clock realignment signal being provided to the oscillator.

13. The loop of claim 12 , wherein a pulse width of the realignment signal is controllable via an input to the pulse generator.

14. The loop of claim 13 , wherein the pulse width of the pulse generator is controlled so as to be:

of shorter length than pulse widths generated by the phase/frequency detector; and

of shorter length than one half of a period of the output wave form.

15. The loop of claim 13 , wherein the input selects which of multiple timing logic gates a selection signal is provided, wherein each of the multiple timing logic gates is associated with a different pulse width of the realignment signal.

16. A method of generating a periodic output waveform, comprising:

comparing a phase and frequency of a reference signal and a feedback signal using a phase/frequency detector;

generating pulses based on first and second outputs of the phase/frequency detector using a charge pump;

generating an output waveform based on the charge pump pulses and a clock realignment signal, the clock realignment signal being based on a third output from the charge pump; and

providing the third output from the charge pump to a third alignment logic gate such that the third output bypasses a filter prior to generating the clock realignment signal.

17. The method of claim 16 , further comprising:

providing each of the first and second outputs of the phase/frequency detector to respective first and second alignment logic gates prior to being used to generate the pulses.

18. The method of claim 17 , wherein the first, second, and third alignment logic gates are a common type of logic gate.

19. A clock generation circuit, comprising:

a charge pump configured to receive a first input signal and a second input signal, the charge pump configured to route the first input signal and the second input signal to respective first and second alignment logic gates, the charge pump configured to generate pulse signals and an output signal based on the first and second input signals;

a realignment circuit configured to generate a realignment signal based on the output signal from the charge pump after the output signal from the charge pump bypasses a filter and is routed through a third alignment logic gate; and

an oscillator configured to produce an output waveform based on the pulse signals and the realignment signal.

20. The clock generation circuit of claim 19 , wherein the first, second, and third alignment logic gates are a common type of logic gate.