Method, system, and apparatus for supporting multiple address spaces to facilitate data movement

1. A method for providing data movement among multiple address spaces, the method comprising:

storing, by a first root port, context data of a second root port, wherein each of the first and second root ports is coupled to a corresponding first and second input/output memory management unit (IOMMU) and a corresponding first and second peripheral component endpoint that are associated with a different respective address space;

receiving, by the first root port, a direct memory access (DMA) request targeted at a memory address space associated with the second IOMMU; and

providing, via the first root port, direct memory access to the memory address space belonging to the second IOMMU in response to the DMA request based on the context data of the second root port.

2. The method according to claim 1 , wherein each of the first and second root ports includes a plurality of registers.

3. The method according to claim 2 , further comprising:

synchronizing, by the first root port, the plurality of registers of the first root port with a plurality of registers of the second root port.

4. The method according to claim 3 , wherein synchronizing the plurality of registers of the first root port with the plurality of registers of the second root port includes:

initializing, by the first root port, the plurality of registers of the first root port with the data of the plurality of registers of the second root port; and

tracking, by the first root port, changes to the plurality of registers of the first and second root ports.

5. The method according to claim 4 , wherein initializing the plurality of registers of the first root port with the data of the plurality of registers of the second root port includes:

receiving, by the first root port from the second root port, a context ID of the second root port.

6. The method according to claim 4 , wherein tracking changes to the plurality of registers of the first and second root ports includes:

transmitting, by the first root port, to the second root port a message when a register of the first root port changes; and

receiving, by the first root port from the second root port, a message when a register of the second root port changes.

7. The method according to claim 6 , wherein the transmitting and receiving is through a register bus.

8. The method according to claim 1 , wherein the DMA request including context data and a function identifier of a function targeted at the memory address space associated with the second IOMMU.

9. The method according to claim 8 , wherein the function is at least one of a physical function and a virtual function of a plurality of virtual functions.

10. A method for supporting multiple memory address spaces to facilitate data movement, the method comprising:

receiving, at a first root port, context data of at least a second root port, wherein each of the first and second root ports is coupled to a corresponding input/output memory management unit (IOMMU) and a corresponding peripheral component endpoint;

synchronizing, by the first root port, a plurality of registers of the first root port with a plurality of registers of the at least the second root port;

receiving, from the corresponding peripheral component endpoint coupled to the first root port, a direct memory access (DMA) request, the DMA request targeted at a memory address space associated with the at least the second IOMMU; and

providing, by the first root port, the DMA request to the first IOMMU based on the context data of the at least second root port.

11. The method according to claim 10 , wherein each IOMMU includes a plurality of memory-mapped input/output (MMIO) registers that map memory address spaces belonging to respective IOMMUs, and

wherein the method further comprises:

accessing, by the first IOMMU, the plurality of MMIO registers of the first IOMMU based on the data of the DMA request provided from the first root port;

accessing, from the first IOMMU, page tables referenced by a context belonging to the second IOMMU of the at least the second root port based on the accessed plurality of MMIO registers;

performing, by the first IOMMU, address translation on the DMA request using the accessed page tables; and

performing, by the first IOMMU, a memory access based on the DMA request and the translated address.

12. The method according to claim 10 , wherein synchronizing the plurality of registers of the first root port with the plurality of registers of the at least the second root port includes:

initializing, by the first root port, the plurality of registers of the first root port with the data of the plurality of registers of the at least the second root port; and

tracking, by the first root port, changes to the plurality of registers of the first and the at least the second root ports.

13. The method according to claim 12 , wherein initializing the plurality of registers of the first root port with the data of the plurality of registers of the at least the second root port includes:

receiving, by the first root port from the at least the second root port, a context ID of the at least the second root port and address of the at least the second root port.

14. The method according to claim 12 , wherein tracking changes to the plurality of registers of the first and the at least the second root ports includes:

transmitting, by the first root port, to the at least the second root port a message when a register of the first root port changes; and

receiving, by the first root port from the at least the second root port, a message when a register of the at least the second root port changes.

15. The method according to claim 14 , wherein the transmitting and receiving is through a register bus.

16. A data processing system, comprising:

a host processor;

a memory;

a data fabric coupled to the host processor and to the memory;

a first input/output memory manage unit (IOMMU) and a second IOMMU, each of the first and second IOMMUs coupled to the data fabric;

a first root port and a second root port, each of the first and second root ports coupled to a corresponding first and second IOMMUs; and

a first peripheral component endpoint and a second peripheral component endpoint, each of the first and second peripheral component endpoints coupled to a corresponding root port of the first and second root ports,

wherein the first root port comprises hardware control logic operative to:

store context data of the second root port;

receive, from the corresponding peripheral component endpoint of the first root port, a direct memory access (DMA) request, the DMA request targeted at a memory address space associated with the at least the corresponding IOMMU of the second root port; and

provide direct memory access to the memory address space belonging to the second IOMMU in response to the DMA request, based on the context data of the second root port.

17. The system according to claim 16 , wherein each of the first and second root ports further comprises a plurality of registers, and

wherein the hardware control logic is further operative to communicate with the plurality of registers of the second root ports via a register bus.

18. The system according to claim 17 , wherein the hardware control logic is operative to:

synchronize the plurality of registers of the first root port with the plurality of registers of the second root port;

access the plurality of registers of the second root port based on the data of the DMA request; and

access, from the second peripheral component endpoints, a function assigned to the memory address space belonging to the second IOMMU based on the accessed plurality of synchronized registers of the first root port.

19. The system according to claim 16 , wherein the memory includes a memory carve out that stores peripheral component endpoint interrupt information.

20. The system according to claim 19 , wherein each of the first and second peripheral component endpoints comprises hardware control logic operative to retrieve, from the memory carve out upon receiving an interrupt request, peripheral component endpoint interrupt information.