Application specific integrated circuit interconnect
Systems and methods for providing Chronos Channel interconnects in an ASIC are provided. Chronos Channels rely on a reduced set of timing assumptions and are robust against delay variations. Chronos Channels transmit data using delay insensitive (DI) codes and quasi-delay-insensitive (QDI) logic. Chronos Channels are insensitive to all wire and gate delay variations, but for those belonging to a few specific forking logic paths called isochronic forks. Chronos Channels use temporal compression in internal paths to reduce the overheads of QDI logic and efficiently transmit data. Chronos Channels are defined by a combination of a DI code, a temporal compression ratio and hardware.
1. A connection between one or more first intellectual property (IP) blocks and one or more receiving IP blocks, the connection comprising:
at least one transmitter (TX) associated with the one or more first IP blocks, the at least one TX comprising one or more bundled data (BD) encoders and one or more temporal compressors, and configured to transform input data signals from the one or more first IP blocks into temporally compressed BD asynchronous signals;
at least one timing dependent communication channel between the at least one TX and a Flow Control block, wherein the BD asynchronous signal from the at least one TX is propagated via the at least one timing dependent communication channel in a self-timed fashion to the Flow Control block;
the Flow Control block comprising a BD Flow Control circuit element configured to propagate the compressed BD asynchronous signals to at least one individual timing dependent communication channels; and
at least one receiver (RX) associated with the one or more receiving IP blocks, at least one RX comprising one or more BD decoders and one or more temporal decompressors; and configured to receive the BD asynchronous signals from the Flow control block and restore the compressed BD asynchronous signals received from the Flow Control block to form duplicates of the input data signals,
wherein the one or more temporal compressors receive encoded data signals from the one or more BD encoders based on the input data and, to transform the input data signals into one or more temporally compressed BD asynchronous signals, serially distributes portions of the encoded data signals into a plurality of temporal slots of a cycle time based on the temporal compression ratio, wherein the cycle time limits the duration of time for the one or more first IP blocks to transmit the input data signals and the one or more second IP blocks to form the representation of the input signals.