Voltage offset for compute-in-memory architecture

1. An electronic device comprising a compute-in-memory (CIM) array comprising a plurality of columns, wherein:

each column comprises:

a plurality of CIM cells connected to a read bitline;

a plurality of offset cells configured to provide a programmable offset value for the column; and

an analog-to-digital converter (ADC) having the read bitline as a first input and configured to receive the programmable offset value, wherein the ADC is configured to receive, as a second input, the programmable offset value; and

each CIM cell is configured to store a corresponding weight.

2. The electronic device of claim 1 , wherein, for each column:

the plurality of CIM cells is configured to receive a corresponding plurality of input values;

each CIM cell is configured to generate an output based on both the corresponding stored weight and the corresponding input value and to provide the output to the read bitline;

the read bitline is configured to provide a sum of the outputs of the CIM cells to the ADC; and

the ADC is configured to generate and output a digital value corresponding to the provided sum of CIM cell outputs.

3. The electronic device of claim 2 , wherein, for each column:

each offset cell of the plurality of offset cells is configured to store a value and configured to provide its stored value to an offset bitline;

the offset bitline is different from the read bitline;

the offset bitline is not connected to any CIM cell of the plurality of CIM cells;

the offset bitline is configured to sum the values provided by the corresponding offset cells to generate the programmable offset value;

the offset bitline is configured to provide the programmable offset value to the ADC as the second input; and

the ADC is configured to use the programmable offset value to set the reference voltage value for use in generating the digital value corresponding to the provided sum.

4. The electronic device of claim 3 , wherein:

each CIM cell comprises a static random-access memory (SRAM) cell connected to a corresponding capacitor via an input-line transistor controlled by the input value;

the capacitor of each CIM cell is connected to the read bitline via a read-wordline transistor controlled by a corresponding read wordline;

each offset cell comprises an SRAM cell connected to the offset bitline via a corresponding read-wordline transistor controlled by a corresponding read wordline.

5. The electronic device of claim 4 , wherein, for each column:

each CIM cell has a corresponding offset cell;

the read wordline corresponding to the CIM cell is the same as the read wordline corresponding to the corresponding offset cell.

6. The electronic device of claim 2 , wherein, for each column:

each CIM cell is a flexible cell configured to be dynamically programmed to function as a CIM cell; and

each offset cell is a flexible cell configured to be dynamically programmed to function as an offset cell.

7. An electronic device comprising a compute-in-memory (CIM) array comprising a plurality of columns, wherein:

each column comprises:

a plurality of CIM cells connected to a read bitline;

a plurality of offset cells configured to provide a programmable offset value for the column; and

an analog-to-digital converter (ADC) having the read bitline as a first input and configured to receive the programmable offset value, wherein the ADC is configured to receive, as a second input, a reference voltage value;

each CIM cell is configured to store a corresponding weight;

each CIM cell comprises a static random-access memory (SRAM) cell connected to a corresponding capacitor via an input-line transistor controlled by the input value;

the capacitor of each CIM cell is connected to the read bitline via a read-wordline transistor controlled by a corresponding read wordline; and

for each column:

each offset cell of the plurality of offset cells is configured to store a value and configured to provide its stored value to the read bitline;

the programmable offset value is a sum of the stored values of the plurality of offset cells; and

the read bitline is configured to add the programmable offset value to the sum of the outputs of the CIM cells to provide to the ADC as the first input.

8. The electronic device of claim 7 , wherein, for each column,

each offset cell comprises an SRAM cell connected to the offset bitline via a corresponding read-wordline transistor controlled by a corresponding read wordline.

9. The electronic device of claim 7 , wherein, for each column, each offset cell and each CIM cell consist of the same components.

10. A method for an electronic device wherein:

the electronic device comprises a compute-in-memory (CIM) array;

the CIM array comprises a plurality of columns;

each column comprises:

a plurality of CIM cells connected to a read bitline;

a plurality of offset cells; and

an analog-to-digital converter (ADC) having the read bitline as a first input;

the method comprising:

storing a corresponding weight in each CIM cell;

providing, to the ADC, by the plurality of offset values, a programmable offset value for the column, wherein the ADC is configured to receive, as a second input, the programmable offset value.

11. The method of claim 10 , further comprising:

receiving, by the plurality of CIM cells, a corresponding plurality of input values;

generating, by each CIM cell, an output based on both the corresponding stored weight and the corresponding input value;

providing, by each CIM cell, the output to the read bitline;

providing, by the read bitline, a sum of the outputs of the CIM cells to the ADC; and

generating and outputting, by the ADC, a digital value corresponding to the provided sum of CIM cell outputs.

12. The method of claim 11 , further comprising:

storing a corresponding value in each offset cell of the plurality of offset cells;

providing, by each offset cell, its stored value to an offset bitline, wherein the offset bitline is different from the read bitline and the offset bitline is not connected to any CIM cell of the plurality of CIM cells;

generating the programmable offset value, by the offset bitline, by summing the values provided by the corresponding offset cells;

providing to the second input of the ADC, by the offset bitline, the programmable offset value; and

generating the digital value corresponding to the provided sum, by the ADC, using the programmable offset value to set the reference voltage value for the generating.

13. The method of claim 12 , wherein:

each CIM cell comprises a static random-access memory (SRAM) cell connected to a corresponding capacitor via an input-line transistor controlled by the input value;

the capacitor of each CIM cell is connected to the read bitline via a read-wordline transistor controlled by a corresponding read wordline;

each offset cell comprises an SRAM cell connected to the offset bitline via a corresponding read-wordline transistor controlled by a corresponding read wordline.

14. The method of claim 13 , wherein, for each column:

each CIM cell has a corresponding offset cell;

the read wordline corresponding to the CIM cell is the same as the read wordline corresponding to the corresponding offset cell.

15. The method of claim 11 , wherein each CIM cell and each offset cell is a flexible cell, the method further comprising:

dynamically programming each of a first of flexible cells to function as a CIM cell; and

dynamically programming each of a second set of flexible cells to function as an offset cell.