Semiconductor memory devices and memory systems including the same

1. A semiconductor memory device, comprising:

a memory cell array including a plurality of volatile memory cells coupled to a plurality of word-lines and a plurality of bit-lines, the memory cell array including a normal cell region and a parity cell region;

an error correction code (ECC) circuit that is selectively operable in a normal mode and a test mode; and

a control logic circuit configured to control the ECC circuit,

wherein, in the normal mode, the ECC circuit is configured to:

receive a main data including normal data bits from an external device, the main data accompanied by a first command;

using an ECC engine, perform an ECC encoding on the main data to generate a parity data; and

store the main data and the parity data, received from the ECC engine, in the normal cell region and the parity cell region, respectively, and

wherein, in the test mode, the ECC circuit is configured to:

receive a test data including at least one error bit from the external device, the test data accompanied by a second command;

bypass the ECC engine to store the test data in the parity cell region, in a first sub test mode;

bypass the ECC engine to store the test data in one of the normal cell region, in a second sub test mode; and

perform an ECC decoding on the test data and one of the main data and the parity data in response to a read command to provide a decoding result data to the external device.

2. The semiconductor memory device as claimed in claim 1 , wherein the ECC circuit is configured to receive the main data and the test data through a same data input/output pad.

3. The semiconductor memory device as claimed in claim 1 , wherein when the test mode designates the first sub test mode, the ECC circuit is configured to:

receive a test parity data including the at least one error bit as the test data;

store the test parity data in a memory location in which the parity data is stored, in the parity cell region;

read the main data and the test parity data in response to a read command; and

perform the ECC decoding on the main data and the test parity data to output the decoding result data.

4. The semiconductor memory device as claimed in claim 1 , wherein when the test mode designates the second sub test mode, the ECC circuit is configured to:

receive a test main data including the at least one error bit as the test data;

store the test main data in a memory location in which the main data is stored, in the normal cell region;

read the test main data and the parity data in response to a read command; and

perform the ECC decoding on the test main data and the parity data to output the decoding result data.

5. The semiconductor memory device as claimed in claim 4 , wherein the at least one error bit includes one of a single bit error, a double bit error, a symbol error, and a data input/output pad error.

6. The semiconductor memory device as claimed in claim 1 , wherein the second command is activated by a setting a test mode register set.

7. The semiconductor memory device as claimed in claim 1 , wherein the test mode is set by one of a mode register set command, a test mode register set command, and a specified command sequence from the external device.

8. The semiconductor memory device as claimed in claim 1 , wherein the ECC circuit includes:

an ECC engine configured to perform the ECC encoding to generate the parity data in the normal mode and configured to perform the ECC decoding to generate the decoding result data in the test mode;

a demultiplexer configured to, in response to a first selection signal, provide the main data to the ECC engine in the normal mode and select one of a test main data including the at least one error bit and a test parity data including the at least one error bit in the test mode;

a multiplexer configured to select one of the parity data and the test parity data in response to a second selection signal; and

a buffer circuit configured to provide the main data and the parity data to the memory cell array in the normal mode and configured to provide one of the test main data and the test parity data to the memory cell array in the test mode.

9. The semiconductor memory device as claimed in claim 8 , wherein the demultiplexer is configured to select the parity data in the normal mode and select the test parity data in the test mode, in response to the second selection signal.

10. The semiconductor memory device as claimed in claim 8 , wherein the ECC engine is configured to:

perform the ECC decoding on the main data and the test parity data to output the decoding result data when the test mode designates a first sub test mode; and

perform the ECC decoding on the test main data and the parity data to output the decoding result data when the test mode designates a second sub test mode.

11. The semiconductor memory device as claimed in claim 8 , wherein the ECC engine includes:

a memory to store an ECC;

an ECC encoder, coupled to the memory, configured to generate the parity data to generate the parity data; and

an ECC decoder, coupled to the memory, configured to perform the ECC decoding on the main data and the test parity data to generate the decoding result data when the test mode designates a first sub test mode, and perform the ECC decoding on the test main data and the parity data to generate the decoding result data when the test mode designates a second sub test mode.

12. The semiconductor memory device as claimed in claim 1 , wherein the ECC circuit is configured to verify an ECC included in the ECC circuit based on the at least one error bit in the test mode.

13. The semiconductor memory device as claimed in claim 1 , comprising:

at least one buffer die; and

a plurality of memory dies, the plurality of memory dies stacked on the at least one buffer die and conveying data through a plurality of through silicon via (TSV) lines,

wherein each of the plurality of memory dies includes the memory cell array and the ECC circuit.

14. A semiconductor memory device, comprising:

a memory cell array including a plurality of volatile memory cells coupled to a plurality of word-lines and a plurality of bit-lines, the memory cell array including a normal cell region and a parity cell region;

an error correction code (ECC) circuit including a storage, the ECC circuit being selectively operable in a normal mode and a test mode; and

a control logic circuit configured to control the ECC circuit,

wherein, in the normal mode, the ECC circuit is configured to:

receive a main data including normal data bits from an external device, the main data accompanied by a first command;

using an ECC engine, perform an ECC encoding on the main data to generate a parity data; and

store the main data and the parity data, received from the ECC engine, in a selected one of the storage and the memory cell array, and

wherein, in the test mode, the ECC circuit is configured to:

receive a test data including at least one error bit from the external device, the test data accompanied by a second command;

bypass the ECC engine to store the test data in the storage and the memory cell array; and

perform an ECC decoding on the test data and one of the main data and the parity data in response to a read command to provide a decoding result data to the external device.

15. The semiconductor memory device as claimed in claim 1 , wherein the ECC circuit is configured to receive the main data and the test data through a same data input/output pad.

16. The semiconductor memory device as claimed in claim 14 , wherein the ECC circuit is configured to:

when the test mode designates a first sub test mode,

receive a test parity data including the at least one error bit as the test data;

store the test parity data in a memory location in which the parity data is stored, in a parity cell region of the selected one of the storage and the memory cell array;

read the main data and the test parity data in response to a read command; and

perform the ECC decoding on the main data and the test parity data to output the decoding result data, and

when the test mode designates a second sub test mode,

receive a test main data including the at least one error bit as the test data;

store the test main data in a memory location in which the main data is stored, in a normal cell region of the selected one of the storage and the memory cell array;

read the test main data and the parity data in response to the read command; and

perform the ECC decoding on the test main data and the parity data to output the decoding result data.

17. The semiconductor memory device as claimed in claim 14 , wherein the ECC circuit includes:

an ECC engine configured to perform the ECC encoding to generate the parity data in the normal mode and perform the ECC decoding to generate the decoding result data in the test mode;

a multiplexer configured to, in response to a first selection signal, provide the main data to the ECC engine in the normal mode, and select one of a test main data including the at least one error bit and a test parity data including the at least one error bit in the test mode;

a demultiplexer configured to select one of the parity data and the test parity data in response to a second selection signal;

a buffer circuit, connected to the memory cell array; and

a path selection circuit configured to provide the main data and the parity data, or the test main data and the test parity data, to one of the buffer circuit and the storage in response to a third selection signal.

18. A memory system, comprising:

a semiconductor memory device; and

a memory controller configured to control the semiconductor memory device,

wherein the semiconductor memory device includes:

a memory cell array including a plurality of volatile memory cells coupled to a plurality of word-lines and a plurality of bit-lines, the memory cell array including a normal cell region and a parity cell region;

an error correction code (ECC) circuit that is selectively operable in a normal mode and a test mode; and

a control logic circuit configured to control the ECC circuit, wherein, in the normal mode, the ECC circuit is configured to:

receive a main data including normal data bits from the memory controller, the main data accompanied by a first command;

using an ECC engine, perform an ECC encoding on the main data to generate a parity data; and

store the main data and the parity data, received from the ECC engine, in the normal cell region and the parity cell region, respectively, and

wherein, in the test mode, the ECC circuit is configured to:

receive a test data including at least one error bit from the memory controller, the test data accompanied by a second command;

bypass the ECC engine to store the test data in the parity cell region, in a first sub test mode;

bypass the ECC engine to store the test data in one of the normal cell region, in a second sub test mode; and

perform an ECC decoding on the test data and one of the main data and the parity data in response to a read command to provide a decoding result data to the memory controller.

19. The memory system as claimed in claim 18 , wherein the memory controller includes:

an error injection register set configured to store an error bit set including at least one error bit, the error bit set being associated with a data set to be provided to the semiconductor memory device;

a data buffer configured to store the main data to be provided to the semiconductor memory device;

a test data generator configured to generate the test data to be provided to the semiconductor memory device based on the data set and the error bit set;

a multiplexer configured to select one of the main data and the test data in response to a mode signal;

an error log register; and

a central processing unit (CPU) configured to control the error injection register set, the data buffer, and the test data generator, and

wherein the CPU is configured to analyze the decoding result data to record error information based on the at least one error bit in the error log register.

20. The memory system as claimed in claim 19 ,

wherein the data buffer includes a plurality of input registers, and each of the input registers is configured to store a first unit of first data bits corresponding to a burst length of the semiconductor memory device, and

wherein the error injection register set includes:

a plurality of error injection registers, and each of the error injection registers is configured to store a second unit of second data bits corresponding to the first data bits of the first unit; and

a register write circuit configured to change a logic level of one of the second data bits in response to a control of the CPU, in the test mode.