Method of making a semiconductor device, semiconductor device and ring oscillator
A method of fabricating a semiconductor device includes forming a gate structure, a first edge structure and a second edge structure on a semiconductor strip. The method further includes forming a first source/drain feature between the gate structure and the first edge structure. The method further includes forming a second source/drain feature between the gate structure and the second edge structure, wherein a distance between the gate structure and the first source/drain feature is different from a distance between the gate structure and the second source/drain feature. The method further includes implanting a buried channel in the semiconductor strip, wherein the buried channel is entirely below a top-most surface of the semiconductor strip, a maximum depth of the buried channel is less than a maximum depth of the first source/drain feature, and a dopant concentration of the buried channel is highest under the gate structure.
1. A semiconductor device comprising:
a fin extending from a substrate;
a first source/drain feature;
a second source/drain feature;
a gate structure on the fin, wherein a first distance between the gate structure and the first source/drain feature is different from a second distance between the gate structure and the second source/drain feature; and
a buried channel, wherein a top surface of the buried channel is spaced from a top surface of the fin, a highest concentration of dopants of the buried channel is under the gate structure, and a width of the buried channel is less than a width of the fin.
2. The semiconductor device of claim 1 , wherein a maximum depth of the buried channel is less than a maximum depth of the first source/drain feature.
3. The semiconductor device of claim 1 , further comprising an edge structure, wherein the first source/drain feature is between the gate structure and the edge structure.
4. The semiconductor device of claim 3 , wherein the edge structure is partially over an isolation structure.
5. The semiconductor device of claim 1 , further comprising:
a gate contact over the gate structure;
a first contact over the first source/drain feature, wherein the first contact is separated from the gate contact by a third distance; and
a second contact over the second source/drain feature, wherein the second contact is separated from the gate contact by a fourth distance different from the third distance.
6. The semiconductor device of claim 5 , wherein a ratio of the third distance to the fourth distance ranges from about 1.5 to about 4.5.
7. A ring oscillator comprising: a plurality of inverters, wherein a transistor of a first inverter of the plurality of inverters comprises: a semiconductor strip on a substrate; a first source/drain feature; a second source/drain feature; a gate structure on the semiconductor strip, wherein a first distance between the gate structure and the first source/drain feature is different from a second distance between the gate structure and the second source/drain feature; and a buried channel, wherein a top surface of the buried channel is spaced from a top surface of the semiconductor strip, a highest concentration of dopants of the buried channel is under the gate structure, the buried channel has a width less than a width of at least one of the first source/drain feature or the second source drain feature, and a width of the buried channel is less than a width of the semiconductor strip.
8. The ring oscillator of claim 7 , wherein a number of inverters of the plurality of inverters is an odd number.
9. The ring oscillator of claim 7 , wherein the transistor is a p-type transistor.
10. The ring oscillator of claim 7 , wherein the transistor is an n-type transistor.
11. The ring oscillator of claim 7 , wherein a ratio of the first distance to the second distance ranges from about 1.5 to about 4.5.
12. A semiconductor device comprising: a gate structure on a semiconductor strip; a first edge structure on the semiconductor strip, wherein the first edge structure partially over an isolation feature; a second edge structure on the semiconductor strip; a first source/drain feature between the gate structure and the first edge structure; a second source/drain feature between the gate structure and the second edge structure, wherein a distance between the gate structure and the first source/drain feature is different from a distance between the gate structure and the second source/drain feature; and a buried channel in the semiconductor strip, wherein the buried channel is entirely below a top-most surface of the semiconductor strip, a maximum depth of the buried channel is less than a maximum depth of the first source/drain feature, a dopant concentration of the buried channel is highest under the gate structure, and a width of the buried channel is less than a width of the semiconductor strip.
13. The semiconductor device of claim 12 , wherein a top surface of the buried channel a distance of about 2 nanometers (nm) to about 7 nm below the top-most surface of the semiconductor strip.
14. The semiconductor device of claim 12 , wherein the buried channel extends across less than an entire width of the semiconductor strip.
15. The semiconductor device of claim 12 , further comprising:
a first contact over the first source/drain feature; and
a second contact over the second source/drain feature, wherein a top-most surface of the first contact is coplanar with a top-most surface of the second contact.
16. The semiconductor device of claim 15 , further comprising a gate contact over the gate structure, wherein a top-most surface of the gate structure is coplanar with the top-most surface of the first contact.
17. The semiconductor device of claim 12 , wherein the first source/drain feature extends above the top-most surface of the semiconductor strip.
18. The semiconductor device of claim 12 , wherein the second source/drain feature is about 1.5 to about 4.5 times farther from the gate structure than the first source/drain feature is from the gate structure.