Method and structure for forming stairs in three-dimensional memory devices

1. A three-dimensional (3D) memory device, comprising a memory stack comprising a plurality of stairs each comprising interleaved one or more conductor layers and one or more dielectric layers, wherein:

each of the stairs comprises a top conductor layer on a top surface of the stair and at least one conductor layer below the top conductor layer, the top conductor layer comprising (i) a bottom portion in contact with one of the dielectric layers, and (ii) a top portion in contact with the bottom portion and having a flat bottom surface, the bottom portion and the top portion comprise a same metal;

a lateral dimension of the top portion is less than a lateral dimension of the bottom portion;

the flat bottom surface of the top portion laterally exceeds the bottom portion and the at least one conductor layer by a distance; and

side surfaces of the interleaved one or more conductor layers and one or more dielectric layers, except a side surface of the top portion of the top conductor layer, are fully and continuously covered by an insulating portion, wherein the insulating portion is (i) covered by the top portion, (ii) filling up the distance laterally, and (iii) in contact with a top portion of another stair immediately below the stair.

2. The 3D memory device of claim 1 , wherein a top surface of the top portion is higher than the bottom surface of a third stair immediately above the respective stair.

3. The 3D memory device of claim 1 , wherein the distance is in a range of about 0.1 nm to about 20 nm.

4. The 3D memory device of claim 3 , wherein the distance is in a range of about 1 nm to about 10 nm.

5. The 3D memory device of claim 1 , wherein the insulating portion comprises at least one of silicon oxide or a high dielectric constant (high-k) dielectric.

6. The 3D memory device of claim 1 , wherein the plurality of stairs are surrounded by an insulating structure.

7. A three-dimensional (3D) memory device, comprising a memory stack comprising a plurality of stairs each comprising interleaved a plurality of conductor layers and a plurality of dielectric layers forming a plurality of conductor/dielectric pairs, wherein:

each of the stairs comprises a top conductor layer on a top surface of the stair and at least one conductor/dielectric layer pair below the top conductor layer, the top conductor layer comprising (i) a bottom portion in contact with one of the dielectric layers, and (ii) a top portion in contact with the bottom portion and having a flat bottom surface;

the flat bottom surface of the top portion laterally exceeds the bottom portion and the at least one conductor/dielectric layer pair by a distance in a range of about 0.1 nm to about 20 nm; and

side surfaces of the plurality of conductor/dielectric pairs of each stair, except a side surface of the top portion of the top conductor layer, are fully and continuously covered by an insulating portion, wherein the insulating portion is (i) covered by the top portion, (ii) filling up the distance laterally, and (iii) in contact with a top portion of another stair immediately below the stair.

8. The 3D memory device of claim 7 , wherein the distance is in a range of about 1 nm to about 10 nm.

9. The 3D memory device of claim 7 , wherein a lateral dimension of the top portion is less than a lateral dimension of the bottom portion.

10. The 3D memory device of claim 7 , wherein the insulating portion comprises at least one of silicon oxide or a high dielectric constant (high-k) dielectric.

11. The 3D memory device of claim 7 , wherein the memory stack is surrounded by an insulating structure.

12. A three-dimensional (3D) memory device, comprising a memory stack comprising a plurality of stairs each comprising interleaved a plurality of conductor layers and a plurality of dielectric layers, wherein:

each of the stairs comprises a top conductor layer on a top surface of the stair, the top conductor layer comprising (i) a bottom portion in contact with one of the dielectric layers, and (ii) a top portion in contact with the bottom portion and having a flat bottom surface;

each of the stairs comprises an insulating portion in contact with a side surface of the stair, the flat bottom surface of the top portion, more than one conductor layer, and more than one dielectric layer below the top conductor layer in the stair, wherein the insulating portion comprising a high dielectric constant (high-k) dielectric material;

a lateral dimension of the top portion is less than a lateral dimension of the bottom portion;

an end of the top portion that is facing away from the memory stack laterally exceeds the bottom portion by a distance; and

side surfaces of the plurality of stairs, except a side surface of the top portion of the top conductor layer, are fully and continuously covered by an insulating portion, wherein the insulating portion is (i) covered by the top portion, (ii) filling up the distance laterally, and (iii) in contact with a top portion of another stair immediately below the stair.

13. The 3D memory device of claim 12 , wherein the distance is in a range of about 1 nm to about 10 nm.

14. The 3D memory device of claim 12 , wherein the insulating portion is in contact with a top portion of another stair immediately below the respective stair.

15. The 3D memory device of claim 12 , wherein a lateral dimension of the top portion is less than a lateral dimension of the bottom portion.

16. The 3D memory device of claim 12 , wherein a top surface of the top portion is higher than the bottom surface of another stair immediately above the respective stair.