Transparent display panel and transparent display device including the same
In a transparent display panel, a layer of each of a VSS voltage connection line and a VDD voltage connection line as a power line in a display region is different from a layer of a data line and a reference voltage connection line, while each of the VSS voltage connection line and the VDD voltage connection line partially overlaps the data line and the reference voltage connection line. Thus, an overall width of a line region may be reduced. Thus, an area of a pixel circuit region is reduced, such that an area of a transmissive region increases, thereby to increase an overall transmittance of the panel. Further, a width of each of the VSS voltage connection line and the VDD voltage connection line is large while reducing or minimizing an area of the line region in the display region. This reduces or minimizes occurrence of VDD drop or VSS rise, thereby to reduce luminance non-uniformity of the panel.
1. A transparent display panel comprising:
a substrate having a display region including a plurality of light-emitting regions and a plurality of transmissive regions; and
a plurality of line regions on the substrate and extending across the display region, wherein the plurality of line regions include VS S voltage connection lines and VDD voltage connection lines,
wherein alternately-arranged adjacent line regions include alternately-arranged adjacent VSS and VDD voltage connection lines, respectively,
wherein each of the line regions further includes at least one data line and at least one reference voltage connection line, and
wherein a layer of each of the VSS voltage connection line and the VDD voltage connection line is different from a layer of the data line and the reference voltage connection line.
2. The transparent display panel of claim 1 , wherein a width of each of the line regions is defined as a sum of widths of the at least one data line, widths of the at least one reference voltage connection line, and spacings between the at least one data line and the at least one reference voltage connection line.
3. The transparent display panel of claim 1 , wherein an outer contour of each of the plurality of transmissive regions is at least partially curved.
4. The transparent display panel of claim 1 , wherein a width of each of the VSS voltage connection line and the VDD voltage connection line is larger than a width of the data line and is larger than a width of the reference voltage connection line.
5. The transparent display panel of claim 4 , wherein the VSS voltage connection line at least partially overlaps with at least two of the at least one data line and the at least one reference voltage connection line, and
wherein the VDD voltage connection line at least partially overlaps with at least two of the at least one data line and the at least one reference voltage connection line.
6. The transparent display panel of claim 1 , wherein the VSS voltage connection line is disposed above the at least one data line and the at least one reference voltage connection line, and
wherein the VDD voltage connection line is disposed above the at least one data line and the at least one reference voltage connection line.
7. The transparent display panel of claim 1 , wherein the at least one data line is arranged symmetrically around the VSS voltage connection line or the VDD voltage connection line,
wherein the at least one reference voltage connection line is arranged symmetrically around the VSS voltage connection line or the VDD voltage connection line.
8. The transparent display panel of claim 7 , wherein the data line and the reference voltage connection line are formed as a same layer.
9. The transparent display panel of claim 6 , wherein a first planarization layer is disposed between the VSS voltage connection line and the data line, and the reference voltage connection line, and between the VDD voltage connection line and the data line, and the reference voltage connection line, and
wherein a second planarization layer is disposed on the VSS voltage connection line and the VDD voltage connection line.
10. The transparent display panel of claim 1 , wherein a first VSS voltage line and a second VSS voltage line are disposed in the non-display region with the display region interposed therebetween, and
wherein the VSS voltage connection line electrically connects the first VSS voltage line and the second VSS voltage line to each other.
11. The transparent display panel of claim 1 , wherein a first VDD voltage line and a second VDD voltage line are disposed in the non-display region with the display region interposed therebetween, and
wherein the VDD voltage connection line electrically connects the first VDD voltage line and the second VDD voltage line to each other.
12. The transparent display panel of claim 1 , wherein each of the plurality of light-emitting regions includes:
a driving thin-film transistor including an active layer, a gate electrode, a source electrode, and a drain electrode; and
an organic light-emitting element including a first electrode, an organic light-emitting layer, and a second electrode,
wherein the source electrode, the drain electrode, the data line, and the reference voltage connection line are formed on the same layer,
wherein a first planarization layer is disposed on the source electrode, the drain electrode, the data line, and the reference voltage connection line,
wherein a second planarization layer is disposed on the VSS voltage connection line and the VDD voltage connection line, and
wherein the organic light-emitting element is disposed on the second planarization layer.
13. The transparent display panel of claim 12 , wherein each of the plurality of transmissive regions includes a gate insulating layer, a first interlayer insulating layer, a second interlayer insulating layer, the first planarization layer, the second planarization layer, the organic light-emitting layer, and the second electrode.
14. The transparent display panel of claim 1 , wherein a first driving thin-film transistor is disposed on one side to a single line region and is configured to drive a first light-emitting region disposed on one side to the single line region and partially overlapping with the single line region, and
wherein a second driving thin-film transistor is disposed on the other side to the single line region and is configured to drive a second light-emitting region disposed on the other side to the single line region and partially overlapping with the single line region.
15. The transparent display panel of claim 1 , wherein the VS S voltage connection line and the VDD voltage connection line are alternately arranged with each other with the transmissive region interposed therebetween.
16. The transparent display panel of claim 1 , wherein the light-emitting regions includes a first color light-emitting region, a second color light-emitting region, and a third color light-emitting region,
wherein each of the second color light-emitting region and the third color light-emitting region is on a corresponding line region,
wherein the first color light-emitting region is disposed between the second color light-emitting region and the third color light-emitting region,
wherein each of the VSS voltage connection line and the VDD voltage connection line at least partially overlaps with the second color light-emitting region or the third color light-emitting region, and
wherein colors of two light-emitting regions arranged in the same row and at least partially overlapping with the VSS voltage connection line and the VDD voltage connection line respectively are different from each other.
17. The transparent display panel of claim 1 , wherein a plurality of pixel circuit regions are on the substrate, and are electrically connected to the light-emitting regions respectively to drive the light-emitting regions,
wherein the pixel circuit regions includes a first color pixel circuit region electrically connected to the first color light-emitting region, a second color pixel circuit region electrically connected to the second color light-emitting region, and a third color pixel circuit region electrically connected to the third color light-emitting region, and
wherein the first color pixel circuit region is arranged symmetrically to the second color pixel circuit region around the line region interposed therebetween or arranged symmetrically to the third color pixel circuit region around the line region interposed therebetween.
18. The transparent display panel of claim 1 , wherein a driving thin-film transistor of the first color pixel circuit region at least partially overlaps with a pixel electrode of the second or third color light-emitting region disposed on a right side to the first color pixel circuit region,
wherein a driving thin-film transistor of the second color pixel circuit region at least partially overlaps with the pixel electrode of the second color light-emitting region, and
wherein a driving thin-film transistor of the third color pixel circuit region at least partially overlaps with the pixel electrode of the third color light-emitting region.
19. The transparent display panel of claim 1 , wherein the light-emitting regions include a first color light-emitting region, a second color light-emitting region, and a third color light-emitting region,
wherein each of the second color light-emitting region and the third color light-emitting region is on a corresponding line region,
wherein the first color light-emitting region is disposed between the second color light-emitting region and the third color light-emitting region,
wherein each color filter corresponding to a color of each light-emitting region is disposed on each light-emitting region, wherein a black matrix is placed between adjacent color filters, and
wherein the black matrix at least partially overlaps with the line region placed between two transmissive regions adjacent to each other.
20. A display device comprising:
a substrate having a display region including a plurality of light-emitting regions and a plurality of transmissive regions; and
a plurality of line regions on the substrate and extending across the display region,
wherein alternately-arranged adjacent line regions include alternately-arranged adjacent VSS and VDD voltage connection lines, respectively,
wherein each of the line regions includes at least one data line and at least one reference voltage connection line, and
wherein a layer of each of the VSS voltage connection line and the VDD voltage connection line is different from a layer of the data line and the reference voltage connection line.