Semiconductor device and manufacturing method of semiconductor device
There is provided a semiconductor device comprising: a semiconductor substrate including a drift region of a first conductivity type; an emitter region of the first conductivity type provided above the drift region inside the semiconductor substrate and having a doping concentration higher than the drift region; a base region of a second conductivity type provided between the emitter region and the drift region inside the semiconductor substrate; a first accumulation region of the first conductivity type provided between the base region and the drift region inside the semiconductor substrate and having a doping concentration higher than the drift region; a plurality of trench portions provided to pass through the emitter region, the base region and first accumulation region from an upper surface of the semiconductor substrate, and provided with a conductive portion inside; and a capacitance addition portion provided below the first accumulation region to add a gate-collector capacitance thereto.
1. A semiconductor device comprising:
a semiconductor substrate including a drift region of a first conductivity type;
an emitter region of the first conductivity type provided above the drift region inside the semiconductor substrate and having a doping concentration higher than the drift region;
a base region of a second conductivity type provided between the emitter region and the drift region inside the semiconductor substrate;
a first accumulation region of the first conductivity type provided between the base region and the drift region inside the semiconductor substrate and having a doping concentration higher than the drift region;
a plurality of trench portions provided to pass through the emitter region, the base region and the first accumulation region from an upper surface of the semiconductor substrate, and provided with a conductive portion inside;
a bottom region of the second conductivity type provided between the accumulation region at the lowest side and the drift region; and
a second accumulation region of the first conductivity type provided below the first accumulation region between two of the plurality of trench portions, wherein
the plurality of trench portions include a gate trench portion and a dummy trench portion, and
the second accumulation region and the bottom region have a portion that is in contact with both the gate trench portion and the dummy trench Portion.
2. The semiconductor device according to claim 1 , wherein
a peak value of a doping concentration in the bottom region is smaller than a peak value of a doping concentration in the base region.
3. The semiconductor device according to claim 1 , wherein
the bottom region connects trench portions located at both sides of a mesa portion therebetween.
4. The semiconductor device according to claim 1 , wherein
the bottom region is configured to operate in an electrically floating state.
5. The semiconductor device according to claim 1 , wherein
the bottom region is, in a depth direction of the semiconductor substrate, provided in a range of depth that overlaps a range of depth of a gate conductive portion.
6. The semiconductor device according to claim 1 , wherein
the bottom region overlaps in a depth direction at least a part of a bottommost portion of an adjacent one of the plurality of trench portions.
7. The semiconductor device according to claim 1 , wherein
the bottom region is formed in each of a plurality of mesa portions and provided adjacent to respective ones of the plurality of trench portions on both sides of each mesa portion.
8. The semiconductor device according to claim 7 , wherein
the bottom regions in respective adjacent mesa portions have a same thickness in a depth direction.
9. The semiconductor device according to claim 7 , wherein
the bottom regions in respective adjacent mesa portions have different thickness in a depth direction.
10. The semiconductor device according to claim 1 , wherein
at least one of the plurality of trench portions has a lower tapered portion below a first depth position corresponding to a boundary between the first accumulation region and the base region, a width of the lower tapered portion in a direction parallel to the upper surface of the semiconductor substrate at the first depth position being smaller than at a deeper second depth position below the first depth position.
11. The semiconductor device according to claim 10 , wherein
the lower tapered portion is formed over a half or more of a region between a position of the boundary and a trench bottom portion.
12. The semiconductor device according to claim 1 , wherein
at least one trench portion in the plurality of trench portions has an upper tapered portion at an upper side than a first depth position corresponding to a boundary between the first accumulation region and the base region, a width of the upper tapered portion at the first depth position being wider in a direction parallel to the upper surface of the semiconductor substrate than at a shallower second depth position above the first depth position.
13. The semiconductor device according to claim 12 , wherein
the upper tapered portion is formed over a region corresponding to a half or more of a region between a position of the boundary and the upper surface of the semiconductor substrate.
14. The semiconductor device according to claim 1 , wherein
a width W 1 of the gate trench portion at the upper surface of the semiconductor substrate is smaller than a width W 2 at a bottom portion of the gate trench portion.
15. The semiconductor device according to claim 10 , wherein
a width W 1 of the gate trench portion in the upper surface is smaller than a width W 2 at a bottom portion of the gate trench portion.
16. The semiconductor device according to claim 1 , wherein
a maximum of a width W 2 in the gate trench portion is larger than a minimum of a width W 5 of a mesa portion adjacent to the gate trench portion.
17. The semiconductor device according to claim 10 , wherein
a maximum of a width W 2 in the gate trench portion is larger than a minimum of a width W 5 of a mesa portion adjacent to the gate trench portion.
18. The semiconductor device according to claim 1 , wherein
a maximum of a width W 2 in the gate trench portion is larger than a maximum of a width W 3 of a mesa portion adjacent to the gate trench portion.
19. The semiconductor device according to claim 10 , wherein
a maximum of a width W 2 in the gate trench portion is larger than a maximum of a width W 3 of a mesa portion adjacent to the gate trench portion.
20. The semiconductor device according to claim 13 , wherein
a first angle θ 1 of a sidewall of the upper tapered portion is larger than a second angle θ 2 of a sidewall of a lower tapered portion below the first depth position.
21. The semiconductor device according to claim 13 , wherein
a first angle θ 1 of a sidewall of the upper tapered portion is smaller than a second angle θ 2 of a sidewall of a lower tapered portion below the first depth position.
22. The semiconductor device according to claim 1 , wherein
a corner in a bottom portion of at least one of the plurality of trench portions has a curved shape.
23. The semiconductor device according to claim 12 , wherein
a doping concentration of a local minimum portion formed between a peak of the doping concentration of the first accumulation region and a peak of a doping concentration of the second accumulation region formed below the first accumulation region varies continuously.
24. The semiconductor device according to claim 1 , wherein
the first accumulation region is in contact with the base region.
25. The semiconductor device according to claim 1 , wherein
both the first accumulation region and the second accumulation region have a concentration peak in a doping concentration distribution.
26. The semiconductor device according to claim 1 , wherein
a bottom portion of each of the plurality of trench portions in the depth direction passes through the bottom region to directly contact the drift region.