IP Library Granted Patent US 11,552,199
Granted Patent B2
US 11,552,199 · App. 16/383,787 · Granted Jan 10, 2023

High-voltage capacitor for integration into electrical power modules and a method for the manufacture of the same

Inventor: Tobias Erlbacher (Poxdorf, DE)
Assignee: FRAUNHOFER-GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V.
H01L29/945H01L29/66181
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Quick Facts
Patent No.
US 11,552,199
App. No.
16/383,787
Granted
Jan 10, 2023
Kind
B2
Abstract

A high-voltage capacitor for integration into electrical power modules has a silicon layer into which an arrangement of recesses is introduced on a front face. The front face with the recesses is coated with a dielectric layer or dielectric layer sequence, wherein the recesses are filled with an electrically conductive material. The silicon layer bears a contact metallisation on the front face and the rear face for purposes of making electrical contact with the capacitor. A layer of thermal SiO 2 is formed between the silicon layer and the dielectric layer or layer sequence. The dielectric layer or layer sequence has a layer thickness of ≥1000 nm and is formed from a ferroelectric or anti-ferroelectric material. The proposed high-voltage capacitor features a high integration density with a high capacitance and good heat dissipation properties.

Claims (11)

1. A high-voltage capacitor for integration into electrical power modules, which capacitor has a silicon layer into which an arrangement of recesses is introduced on a front face, wherein

the front face, with the recesses, is coated with a dielectric layer or layer sequence, the recesses are filled with an electrically conductive material, and the silicon layer bears a contact metallisation (123a) on the front face and on the rea r face in each case, characterised in that,

a layer of thermal SiO 2 , is formed between the silicon layer and the dielectric layer or layer sequence said layer of thermal SiO 2 being in contact with the dielectric layer or layer sequence, and the dielectric layer or layer sequence has a layer thickness of ≥1000 nm is formed of a ferroelectric or anti-ferroelectric material, or contains a ferroelectric or anti-ferroelectric material.

2. The high-voltage capacitor in accordance with claim 1 , characterised in that a further dielectric layer, in particular of SiO 2 or Si 3 N 4 , is formed between the dielectric layer or layer sequence and the contact metallisation on the front face.

3. The high-voltage capacitor in accordance with claim 1 , characterised in that the electrically conductive material is at least partially polysilicon or a metallic material.

4. The high-voltage capacitor in accordance with claim 1 , characterised in that the dielectric layer sequence comprises a plurality of dielectric layers of the ferroelectric or anti-ferroelectric material, with intermediate dielectric layers of one or a plurality of other materials, in particular SiO 2 and/or Si 3 N 4 .

5. The high-voltage capacitor in accordance with claim 1 , characterised in that the recesses are trenches.

6. The high-voltage capacitor in accordance with claim 1 , characterised in that the contact metallisation has a thickness by means of which a local self-healing of the capacitor is achieved in the event of leakage currents occurring.

7. The high-voltage capacitor in accordance with claim 1 , further comprising,

a substrate of an electrical power module which carries the high-voltage capacitor as a damping component or as an intermediate circuit capacitor.

8. A method for the manufacture of a high-voltage capacitor in accordance with claim 1 , in which the dielectric layer or layer sequence is produced by conformal deposition.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 30, 2019
From: ERLBACHER, TOBIAS
To: FRAUNHOFER-GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V.
Reel/Frame 049318/0324 →
Priority Claims (1)
DE 10 2018 206 061.4 · Apr 20, 2018 · national
Continuity (1)
Related Publication 20190326449A1 · Oct 24, 2019