Timing skew mismatch calibration for time interleaved analog to digital converters
A time-interleaved analog to digital converter (TI-ADC) includes a first sub-ADC configured to sample and convert an input analog signal to generate a first digital signal and a second sub-ADC configured to sample and convert said input analog signal to generate a second digital signal. Sampling by the second sub-ADC occurs with a time skew mismatch. A multiplexor interleaves the first and second digital signals to generate a third digital signal. A time skew mismatch error determination circuit processes the first and second digital signals to generate a time error corresponding to the time skew mismatch. A slope value of said third digital signal is determined and multiplied by the time error to generate a signal error. The signal error is summed with the third digital signal to generate a digital output signal which eliminates the error due to the time skew mismatch. This correction is performed in real time.
1. A time-interleaved analog to digital converter (TI-ADC), comprising:
a first sub-ADC configured to sample and convert an input analog signal to generate a first digital signal;
a second sub-ADC configured to sample and convert said input analog signal to generate a second digital signal, wherein sampling by said second sub-ADC occurs with a time skew mismatch;
a multiplexor configured to interleave the first and second digital signals to generate a third digital signal;
a time skew mismatch error (TSME) determination circuit configured to process the first and second digital signals to generate a time error corresponding to said time skew mismatch;
a slope extraction circuit configured to process the third digital signal to determine a slope value of said third digital signal;
a multiplication circuit configured to multiply the time error by the slope value to generate a signal error; and
a summation circuit configured to sum the signal error with the third digital signal to generate a digital output signal.
2. The TI-ADC of claim 1 , wherein the first and second sub-ADCs each sample at a sub-sample rate of a converter sample rate, but sample with a phase offset that is a function of a number of sub-ADCs which are included in the TI-ADC.
3. The TI-ADC of claim 2 , wherein the multiplexor interleaves the first and second digital signals at the converter sample rate.
4. The TI-ADC of claim 1 , wherein the slope extraction circuit determines the slope value for second digital signal samples within said third digital signal.
5. The TI-ADC of claim 4 , wherein the summation circuit sums the signal error with the second digital signal samples within said third digital signal.
6. The TI-ADC of claim 1 , wherein the TSME determination circuit comprises:
an interpolation circuit configured to generate a plurality of interpolated samples from the first digital signal;
a comparison circuit configured to compare the plurality of interpolated samples to the second digital signal and identify a number of interpolated samples between a time of the second digital signal and a time of a closest one of the plurality of interpolated samples to the second digital signal; and
a conversion circuit configured to generate the time error from said identified number of interpolated samples.
7. The TI-ADC of claim 6 , wherein the interpolation circuit comprises:
an upsampling circuit configured to upsample the first digital signal; and
a filtering circuit configured to filter the upsampled the first digital signal to generate the plurality of interpolated samples.
8. The TI-ADC of claim 7 , wherein the filtering circuit is a polyphase circuit, and wherein the polyphase circuit is configured to generate the plurality of interpolated samples to include a limited number of interpolated samples located around the time of the second digital signal.
9. The TI-ADC of claim 8 , wherein the limited number is substantially smaller than a rate of the upsampling.
10. The TI-ADC of claim 1 , wherein the signal error is a first order estimation of an error in the second digital signal due to the time skew mismatch.
11. A time-interleaved analog to digital converter (TI-ADC), comprising:
a first sub-ADC configured to sample and convert an input analog signal to generate a first digital signal;
a second sub-ADC configured to sample and convert said input analog signal to generate a second digital signal, wherein sampling by said second sub-ADC occurs with a first time skew mismatch;
a third sub-ADC configured to sample and convert said input analog signal to generate a third digital signal, wherein sampling by said third sub-ADC occurs with a second time skew mismatch;
a first multiplexor configured to interleave the first, second and third digital signals to generate a fourth digital signal;
a first time skew mismatch error (TSME) determination circuit configured to process the first and second digital signals to generate a first time error corresponding to said first time skew mismatch;
a second TSME determination circuit configured to process the first and third digital signals to generate a second time error corresponding to said second time skew mismatch;
a second multiplexor configured to interleave the first and second time errors generate a time error signal;
a slope extraction circuit configured to process the third digital signal to determine a slope value of said third digital signal;
a multiplication circuit configured to multiply the time error signal by the slope value to generate a signal error; and
a summation circuit configured to sum the signal error with the fourth digital signal to generate a digital output signal.
12. The TI-ADC of claim 11 , wherein the first, second and third sub-ADCs each sample at a sub-sample rate of a converter sample rate, but sample with a phase offset that is a function of a number of sub-ADCs which are included in the TI-ADC.
13. The TI-ADC of claim 12 , wherein the first multiplexor interleaves the first, second and third digital signals at the converter sample rate.
14. The TI-ADC of claim 11 , wherein the slope extraction circuit determines the slope value for second and third digital signal samples within said fourth digital signal.
15. The TI-ADC of claim 14 , wherein the summation circuit sums the signal error with the second and third digital signal samples within said fourth digital signal.
16. The TI-ADC of claim 11 , wherein each of the first and second TSME determination circuits comprises:
an interpolation circuit configured to generate a plurality of interpolated samples from the first digital signal;
a comparison circuit configured to compare the plurality of interpolated samples to the second or third digital signal and identify a number of interpolated samples between a time of the second or third digital signal and a time of a closest one of the plurality of interpolated samples to the second or third digital signal; and
a conversion circuit configured to generate the time error from said identified number of interpolated samples.
17. The TI-ADC of claim 16 , wherein the interpolation circuit comprises:
an upsampling circuit configured to upsample the first digital signal; and
a filtering circuit configured to filter the upsampled the first digital signal to generate the plurality of interpolated samples.
18. The TI-ADC of claim 17 , wherein the filtering circuit is a polyphase circuit, and wherein the polyphase circuit is configured to generate the plurality of interpolated samples to include a limited number of interpolated samples located around the time of the second or third digital signal.
19. The TI-ADC of claim 18 , wherein the limited number is substantially smaller than a rate of the upsampling.
20. The TI-ADC of claim 11 , wherein the signal error is a first order estimation of an error in the second or third digital signal due to the first or second time skew mismatch, respectively.
21. A method for time-interleaved analog to digital conversion, comprising:
sampling and converting an input analog signal to generate a first digital signal;
sampling and converting said input analog signal to generate a second digital signal, wherein sampling by said second sub-ADC occurs with a time skew mismatch;
interleaved selecting of the first and second digital signals to generate a third digital signal;
determining from the first and second digital signals a time error corresponding to said time skew mismatch;
processing the third digital signal to determine a slope value of said third digital signal;
multiplying the time error by the slope value to generate a signal error; and
summing the signal error with the third digital signal to generate a digital output signal.
22. The method of claim 21 , wherein sampling of the input signal to produce the first and second digital signals occurs with a phase offset.
23. The method of claim 21 , wherein interleaved selecting is made at a rate of the sampling.
24. The method of claim 21 , wherein processing to determine the slope value is performed for second digital signal samples within said third digital signal.
25. The method of claim 24 , wherein summing comprises summing the signal error with the second digital signal samples within said third digital signal.
26. The method of claim 21 , wherein determining the time error comprises:
generating a plurality of interpolated samples from the first digital signal;
comparing the plurality of interpolated samples to the second digital signal;
identifying a number of interpolated samples between a time of the second digital signal and a time of a closest one of the plurality of interpolated samples to the second digital signal; and
generating the time error from said identified number of interpolated samples.
27. The method of claim 26 , wherein generating the plurality of interpolated samples comprises:
upsampling the first digital signal; and
filtering the upsampled the first digital signal to generate the plurality of interpolated samples.
28. The method of claim 27 , wherein filtering comprises performing a polyphase filtering to generate the plurality of interpolated samples to include a limited number of interpolated samples located around the time of the second digital signal.
29. The method of claim 28 , wherein the limited number is substantially smaller than a rate of the upsampling.
30. The method of claim 21 , wherein the signal error is a first order estimation of an error in the second digital signal due to the time skew mismatch.