IP Library Granted Patent US 11,555,850
Granted Patent B2
US 11,555,850 · App. 17/510,730 · Granted Jan 17, 2023

Error detection device and error detection method

Inventor: Hisao Kidokoro (Kanagawa, JP)
Assignee: ANRITSU CORPORATION
G01R31/3171G01R31/319G01R31/3183H03M13/35H04L1/00
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Quick Facts
Patent No.
US 11,555,850
App. No.
17/510,730
Granted
Jan 17, 2023
Kind
B2
Abstract

It is possible to know a guideline for adjusting the levels of three voltage thresholds of a PAM4 signal. An error detection device receives a measurement pattern including a pseudo random pattern having equal appearance frequencies of four levels, decodes the measurement pattern into a most significant bit sequence signal MSB and a least significant bit sequence signal LSB, based on three voltage thresholds Vth1, Vth2, and Vth3, identifies and counts, by a level counting unit, the four levels of the measurement pattern, based on the most significant bit sequence signal MSB and the least significant bit sequence signal LSB, and displays numerical values or bar graphs indicating ratios of the appearance frequencies of the four levels of the measurement pattern so as to be in the same order as waveform levels of the measurement pattern, based on a result of the counting.

Claims (10)

1. An error detection device comprising:

a receiver configured to receive a measurement pattern including a pseudo random pattern having equal appearance frequencies of four levels from a device under test, and configured to decode the measurement pattern into a most significant bit sequence signal and a least significant bit sequence signal, based on three voltage thresholds for identifying voltages of the four levels of the measurement pattern;

a processor configured to identify the four levels of the measurement pattern, based on the decoded most significant bit sequence signal and least significant bit sequence signal, and configured to count the number of each level; and

a display configured to display at least one of numerical values or bar graphs indicating ratios of the appearance frequencies of the four levels of the measurement pattern, based on a result of counting by the processor.

2. The error detection device according to claim 1 , wherein the numerical values or the bar graphs indicating the ratios of the appearance frequencies of the four levels of the measurement pattern are in the same order as waveform levels of the measurement pattern.

3. An error detection method comprising:

receiving a measurement pattern including a pseudo random pattern having equal appearance frequencies of four levels from a device under test, and decoding the measurement pattern into a most significant bit sequence signal and a least significant bit sequence signal, based on three voltage thresholds for identifying voltages of the four levels of the measurement pattern;

by a processor of an error detection device, identifying the four levels of the measurement pattern, based on the decoded most significant bit sequence signal and least significant bit sequence signal, and counting the number of each level; and

displaying at least one of numerical values or bar graphs indicating ratios of the appearance frequencies of the four levels of the measurement pattern, based on a result of the counting.

4. The error detection method according to claim 3 , wherein the numerical values or the bar graphs indicating the ratios of the appearance frequencies of the four levels of the measurement pattern are in the same order as waveform levels of the measurement pattern.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 26, 2021
From: KIDOKORO, HISAO
To: ANRITSU CORPORATION
Reel/Frame 057917/0312 →
Priority Claims (1)
JP JP2021-012222 · Jan 28, 2021 · national
Continuity (1)
Related Publication 20220236323A1 · Jul 28, 2022