Processing of data

1. A method, comprising:

identifying data to be processed;

processing the identified data using an error code with a processing circuit to:

correct 1-bit errors,

correct adjacent 2-bit errors, and

detect nonadjacent 2-bit errors,

outputting the processed identified data when the identified data, upon processing, contains a corrected 1-bit error or a corrected adjacent 2-bit error; and

outputting an error indication indicating that the identified data, upon processing, contains a nonadjacent 2-bit error,

wherein the error code comprises an H-matrix with n columns and m rows,

wherein the columns of the H-matrix are different,

wherein component-by-component XOR sums of adjacent columns of the H-matrix are different from one another and from all columns of the H-matrix, and

wherein component-by-component XOR sums of nonadjacent columns of the H-matrix are different from all columns of the H-matrix and from all component-by-component XOR sums of adjacent columns of the H-matrix.

2. The method as claimed in claim 1 , wherein a number of all components of a column of the H-matrix is less than the smallest whole number that is greater than 2·log 2 n.

3. The method as claimed in claim 1 , wherein the error code is an error-detecting code, or an error-correcting and error-detecting code.

4. The method as claimed in claim 1 , wherein at least two component-by-component XOR sums of nonadjacent columns of the H-matrix are not different.

5. The method as claimed in claim 1 , wherein the error code has a length of n bits with m check bits and n-m payload bits.

6. The method as claimed in claim 1 , further comprising determining a syndrome generator for forming an m-component error syndrome in accordance with the H-matrix.

7. The method as claimed in claim 6 , wherein the syndrome generator is implemented as a combinatorial circuit having n inputs and m outputs.

8. The method as claimed in claim 6 , further comprising forming correction values for erroneous bit positions using a correction value formation unit that uses the m-component error syndrome provided by the syndrome generator.

9. The method as claimed in claim 1 , wherein the H-matrix is part of an extended H-matrix.

10. The method as claimed in claim 9 , wherein the extended H-matrix is determined by:

duplicating the H-matrix into an original H-matrix and a duplicate H-matrix, wherein an intermediate column having m zeroes is inserted between the original H-matrix and the duplicate H-matrix,

wherein the original H-matrix has two rows having n zeroes added to it,

wherein the duplicate H-matrix has one row having n ones and a further row added to it, wherein the further row is determined by:

a bit combination comprising n bits according to 1010 . . . 10, if n is even-numbered,

or

a bit combination comprising n bits according to 1010 . . . 1, if n is odd-numbered, and

wherein the intermediate column comprising m zeroes has one column [0,1] T added to it.

11. The method as claimed in claim 1 , wherein the H-matrix is adapted by deleting at least one first column and/or at least one last column.

12. The method as claimed in claim 1 , wherein the H-matrix is modified by a linear combination of its rows.

13. The method as claimed in claim 1 , wherein the processing of the data comprises writing to a memory or reading from a memory.

14. An apparatus for processing data using an error code, wherein the error code has an H-matrix with n columns and m rows, wherein the apparatus comprises:

a memory circuit comprising instructions; and

a processing circuit that is configured to retrieve and execute the instructions, and upon execution of the instructions the processing circuit is configured to:

determine the error code in accordance with the H-matrix, and

use the determined error code to process identified data to:

correct 1-bit errors,

correct adjacent 2-bit errors, and

detect nonadjacent 2-bit errors,

output the processed identified data when the identified data, upon processing, contains a corrected 1-bit error or a corrected adjacent 2-bit error; and

output an error indication indicating that the identified data, upon processing, contains a nonadjacent 2-bit error,

wherein the columns of the H-matrix are different,

wherein component-by-component XOR sums of adjacent columns of the H-matrix are different from one another and from all columns of the H-matrix, and

wherein component-by-component XOR sums of nonadjacent columns of the H-matrix are different from all columns of the H-matrix and from all component-by-component XOR sums of adjacent columns of the H-matrix.

15. The apparatus as claimed in claim 14 , wherein the processing circuit comprises a syndrome generator configured to output syndromes based on the H-matrix.

16. The apparatus as claimed in claim 14 , wherein the processing of the data comprises writing to the memory circuit or reading from the memory circuit.

17. The apparatus as claimed in claim 14 , wherein a number of all components of a column of the H-matrix is less than the smallest whole number that is greater than 2·log 2 n.

18. The apparatus as claimed in claim 14 , wherein at least two component-by-component XOR sums of nonadjacent columns of the H-matrix are not different.