Semiconductor device structure and methods of forming the same

1. An interconnection structure, comprising:

a dielectric layer;

a first conductive feature disposed in the dielectric layer;

a conductive layer disposed over the dielectric layer, wherein the conductive layer includes a first portion and a second portion adjacent the first portion, and the second portion of the conductive layer is disposed over the first conductive feature;

a first barrier layer in contact with the first portion of the conductive layer;

a second barrier layer in contact with the second portion of the conductive layer; and

a support layer in contact with the first and second barrier layers, wherein an air gap is located between the first and second barrier layers, and the support layer is a continuous layer disposed over the air gap.

2. The interconnection structure of claim 1 , wherein the first and second barrier layers each comprises a refractory metal nitride.

3. The interconnection structure of claim 1 , further comprising a first dielectric material disposed on the support layer, wherein the first dielectric material includes a surface that is substantially co-planar with a surface of the first portion of the conductive layer.

4. The interconnection structure of claim 3 , further comprising a second dielectric material disposed over the first portion of the conductive layer and the first dielectric material.

5. The interconnection structure of claim 4 , further comprising a second conductive feature disposed in the second dielectric material, wherein the second conductive feature is disposed over the second portion of the conductive layer.

6. The interconnection structure of claim 1 , further comprising a glue layer disposed between the dielectric layer and the conductive layer.

7. A structure, comprising:

a device layer; and

an interconnection structure disposed over the device layer, wherein the interconnection structure comprises:

a dielectric layer;

a first conductive feature disposed in the dielectric layer;

a conductive layer disposed over the dielectric layer, wherein the conductive layer includes a first portion and a second portion adjacent the first portion, and the second portion of the conductive layer is disposed over the first conductive feature;

a first barrier layer in contact with the first portion of the conductive layer;

a second barrier layer in contact with the second portion of the conductive layer, wherein the first and second barrier layers are separated by an air gap;

a first dielectric material disposed over the air gap, wherein the first dielectric material includes a surface substantially co-planar with a surface of the second portion of the conductive layer;

a metal oxide layer disposed on the surface of the first dielectric material; and

a second conductive feature disposed over the surface of the second portion of the conductive layer, wherein the second conductive feature is disposed adjacent and over the metal oxide layer.

8. The structure of claim 7 , wherein the interconnection structure further comprises a first cap layer disposed on the first conductive feature.

9. The structure of claim 8 , wherein the interconnection structure further comprises a glue layer disposed on the first cap layer, wherein the second portion of the conductive layer is disposed on the glue layer.

10. The structure of claim 9 , wherein the interconnection structure further comprises a second cap layer disposed on the first portion of the conductive layer.

11. The structure of claim 10 , wherein the interconnection structure further comprises an etch stop layer disposed on the second cap layer and the metal oxide layer.

12. The structure of claim 11 , wherein the interconnection structure further comprises a second dielectric material disposed on the etch stop layer, wherein the second conductive feature is disposed in the second dielectric material.

13. The structure of claim 7 , wherein the device layer comprises one or more transistors.

14. The structure of claim 13 , wherein the one or more transistors comprise a source/drain epitaxial feature.

15. The structure of claim 14 , wherein the first conductive feature is electrically connected to the source/drain epitaxial feature.

16. A method, comprising:

forming a conductive layer over a dielectric layer;

forming one or more openings in the conductive layer to expose portions of the dielectric layer, wherein the one or more openings separates the conductive layer into one or more portions;

forming a first blocking layer on the exposed portions of the dielectric layer;

forming barrier layers in contact with the portions of the conductive layer;

removing the first blocking layer;

forming a degradable layer in each of the one or more openings;

forming a support layer in each of the one or more openings;

removing the degradable layer to form an air gap in each of the one or more openings;

forming a first dielectric material on the support layer;

forming a cap layer on each portion of the conductive layer;

forming a second blocking layer on each cap layer;

forming a metal oxide layer on the first dielectric material; and

removing the second blocking layer.

17. The method of claim 16 , further comprising recessing the degradable layer prior to forming the support layer.

18. The method of claim 17 , further comprising performing a planarization process after forming the first dielectric material but before forming the cap layer, wherein surfaces of the portions of the conductive layer are substantially co-planar with a surface of the first dielectric material.

19. The method of claim 18 , further comprising:

forming an etch stop layer on the cap layer and the metal oxide layer; and

forming a second dielectric material on the etch stop layer.

20. The method of claim 19 , further comprising forming a conductive feature in the second dielectric material, wherein the conductive feature is disposed adjacent and over one of the metal oxide layer.