Monolithic 3D integration inter-tier vias insertion scheme and associated layout structure
A 3D-IC includes a first tier device and a second tier device. The first tier device and the second tier device are vertically stacked together. The first tier device includes a first substrate and a first interconnect structure formed over the first substrate. The second tier device includes a second substrate, a doped region formed in the second substrate, a dummy gate formed over the substrate, and a second interconnect structure formed over the second substrate. The 3D-IC also includes an inter-tier via extends vertically through the second substrate. The inter-tier via has a first end and a second end opposite the first end. The first end of the inter-tier via is coupled to the first interconnect structure. The second end of the inter-tier via is coupled to one of: the doped region, the dummy gate, or the second interconnect structure.
1. A method, comprising:
receiving a layout plan for an Integrated Circuit (IC) cell;
splitting the layout plan into a first portion of the IC cell and a second portion of the IC cell;
implementing the first portion of the IC cell on a first tier device;
implementing the second portion of the IC cell on a second tier device; and
electrically coupling the first tier device with the second tier device.
2. The method of claim 1 , wherein the implementing the first portion of the IC and the implementing the second portion of the IC the first portion of the IC are performed such that the first tier device is stacked on top of the second tier device.
3. The method of claim 1 , wherein the electrically coupling comprises implementing a plurality of inter-tier vias (ITVs) between the first tier device and the second tier device.
4. The method of claim 3 , wherein the ITVs are not included in the received layout plan for the IC cell.
5. The method of claim 3 , wherein the implementing the plurality of ITVs comprises: electrically coupling a first end of each of the ITVs with the first tier device and electrically coupling a second end of each of the ITVs with the second tier device.
6. The method of claim 5 , wherein:
the electrically coupling the first end of each of the ITVs comprises electrically coupling the first end of each of the ITVs to a first metal line of a first interconnect structure of the first tier device; and
the electrically coupling the second end of each of the ITVs comprises electrically coupling the second end of each of the ITVs to a second metal line of a second interconnect structure of the first tier device.
7. The method of claim 5 , wherein the implementing the plurality of ITVs comprises implementing the ITVs in a staggered arrangement in a top view.
8. The method of claim 3 , further comprising: before the splitting, stretching the layout plan for the IC cell to create an extra space in the stretched layout plan, wherein the plurality of ITVs are implemented in the extra space.
9. The method of claim 1 , wherein the splitting is performed such that the first portion of the IC cell is symmetrical to the second portion of the IC cell.
10. The method of claim 1 , wherein the splitting is performed such that the first portion of the IC cell is asymmetrical to the second portion of the IC cell.
11. The method of claim 1 , wherein the splitting comprises folding the second portion of the IC cell by 180 degrees before implementing the second portion of the IC cell on the second tier device.
12. The method of claim 1 , wherein:
the layout plan includes a first power rail and a first ground rail;
the splitting comprises splitting the first power rail into a second power rail and a third power rail and splitting the first ground rail into a second ground rail and a third ground rail;
the implementing the first portion of the IC comprises implementing the second power rail and the second ground rail on the first tier device; and
the implementing the second portion of the IC comprises implementing the third power rail and the third ground rail on the second tier device.
13. The method of claim 1 , further comprising: performing a layout rule check on the layout plan after the splitting.
14. A method, comprising:
accessing a layout plan of an Integrated Circuit (IC) cell;
splitting the layout plan into a first region of the IC cell and a second region of the IC cell;
implementing the first region of the IC cell on a first tier device;
implementing the second region of the IC cell on a second tier device; and
electrically coupling, through one or more inter-tier vias (ITVs), the first tier device with the second tier device.
15. The method of claim 14 , wherein the accessed layout plan of the IC cell is free of the ITVs.
16. The method of claim 14 , wherein the first tier device and the second tier device are located at different levels.
17. The method of claim 14 , wherein:
a first end of each of the one or more ITVs is electrically connected to a respective first metal line of the first tier device; and
a second end of each of the one or more ITVs is electrically connected to a respective second metal line of the second tier device.
18. The method of claim 14 , wherein the electrically coupling is performed using a plurality of ITVs that have a staggered arrangement in a top view.
19. A method, comprising:
accessing a layout plan of an Integrated Circuit (IC) cell;
dividing the layout plan into a first portion of the IC cell and a second portion of the IC cell;
implementing the first portion of the IC cell on a first tier device located at a first level;
implementing the second portion of the IC cell on a second tier device located at a second level different from the first level; and
electrically coupling, through a plurality of inter-tier vias (ITVs) that have a staggered arrangement in a top view, the first tier device with the second tier device, wherein the accessed layout plan of the IC cell lacks the ITVs.
20. The method of claim 19 , further comprising: before the dividing, stretching the layout plan of the IC cell, thereby creating an extra space in the stretched layout plan, wherein the plurality of ITVs are implemented in the extra space.