Semiconductor package for improving reliability
A semiconductor package includes a chip level unit including a semiconductor chip; a medium level unit; and a solder ball unit. The solder ball unit is to be connected to a circuit substrate. The medium level unit includes: a wiring pad layer on a first protection layer; a second protection layer including a pad-exposing hole on the first protection layer, a post layer in the pad-exposing hole on the wiring pad layer; and a third protection layer including a post-exposing hole on the second protection layer. A width or diameter of the post-exposing hole is smaller than a width or diameter of the pad-exposing hole; and a barrier layer is disposed in the post-exposing hole on the post layer. The solder ball unit includes a solder ball on the barrier layer.
1. A semiconductor package comprising:
a chip level portion comprising a semiconductor chip;
a medium level portion on the chip level portion; and
a solder ball portion on the medium level portion, wherein the solder ball portion is configured to be connected to a circuit substrate,
wherein the medium level portion comprises:
a wiring pad layer on a first protection layer, the first protection layer being a layer of a plurality of protection layers and being directly adjacent to the chip level portion;
a second protection layer comprising a pad-exposing hole exposing the wiring pad layer on the first protection layer, the second protection layer being an intermediate portion of the plurality of protection layers;
a post layer in the pad-exposing hole on the wiring pad layer;
a third protection layer on the second protection layer and comprising a post-exposing hole on the second protection layer and exposing the post layer, the third protection layer corresponding to an outer protection layer of the plurality of protection layers, wherein a width or diameter of the post-exposing hole is less than a width or diameter of the pad-exposing hole; and
a barrier layer in the post-exposing hole on the post layer,
wherein the solder ball portion comprises a solder ball on the barrier layer.
2. The semiconductor package of claim 1 , wherein a width or diameter of the post layer is less than or equal to a width diameter of the barrier layer.
3. The semiconductor package of claim 1 , wherein a first width or first diameter of the post-exposing hole at the post layer is less than a second width or second diameter of the post-exposing hole adjacent to the solder ball, and a first width or first diameter of the barrier layer at a first surface of the barrier layer is less than a second width or second diameter of the barrier layer at a second surface of the barrier layer opposite the first surface.
4. The semiconductor package of claim 1 , wherein a modulus of elasticity of the second protection layer is greater than a modulus of elasticity of the third protection layer.
5. The semiconductor package of claim 1 , wherein the post layer has a single continuous structure of a circular or ring shape in a plan view.
6. The semiconductor package of claim 1 , wherein the post layer has a single continuous structure in which a width of a first surface of the post layer is the same as a width of a second surface of the post layer opposite the first surface.
7. The semiconductor package of claim 1 , wherein the post layer has a single continuous structure in which a width of a first surface of the post layer is greater than a width of a second surface of the post layer opposite the first surface.
8. The semiconductor package of claim 1 , wherein the post layer comprises a plurality of sub-post layers having circular shapes and arranged along an edge of the post-exposing hole in a plan view.
9. The semiconductor package of claim 1 , wherein a surface of the post layer that contacts the barrier layer is coplanar with a surface of the second protection layer.
10. A semiconductor package comprising:
a semiconductor chip;
a first protection layer on the semiconductor chip;
a redistribution pad layer on the first protection layer;
a second protection layer comprising a pad-exposing hole exposing the redistribution pad layer on the redistribution pad layer;
a post layer in the pad-exposing hole on the redistribution pad layer;
a third protection layer comprising a post-exposing hole on the post layer and exposing the post layer, wherein the post-exposing hole is smaller than the pad-exposing hole;
a barrier layer in the pad-exposing hole on the post layer; and
a solder layer on the barrier layer,
wherein a modulus of elasticity of the second protection layer is greater than a modulus of elasticity of the third protection layer.
11. The semiconductor package of claim 10 , wherein the barrier layer extends outward from the post-exposing hole on the third protection layer, and a maximum width or diameter of the post layer is equal to or less than a minimum width or diameter of the barrier layer on the third protection layer.
12. The semiconductor package of claim 10 , wherein the second protection layer comprises a material having a modulus of elasticity that is greater than or equal to a modulus of elasticity of the first protection layer.
13. The semiconductor package of claim 10 , wherein the post layer has a circular shape in a plan view, and the post layer has a single pillar in which widths (or diameters) of upper and lower portions are identical to each other.
14. The semiconductor package of claim 10 , wherein the post layer comprises a plurality of sub-post layers arranged in a circular shape along an edge of the post-exposing hole in a plan view.
15. The semiconductor package of claim 10 , wherein the post layer has a circular shape in a plan view, and an upper surface of the post layer is a curved surface.
16. A semiconductor package comprising:
a semiconductor chip comprising a chip circuit layer on a semiconductor substrate, and a chip pad connected to the chip circuit layer;
a first protection layer on the chip circuit layer and the chip pad;
a redistribution structure comprising a redistribution layer including a first portion penetrating the first protection layer and connected to the chip pad, the first portion extending from the chip pad on the first protection layer in a horizontal direction, and a second portion at one end portion of the redistribution layer;
a second protection layer comprising a pad-exposing hole on the redistribution structure and exposing the second portion of the redistribution layer;
a post layer in the pad-exposing hole on the redistribution structure;
a third protection layer comprising a post-exposing hole on the post layer and exposing the post layer, wherein the post-exposing hole is smaller than the pad-exposing hole;
a barrier layer in the post-exposing hole on the post layer; and
a solder layer on the barrier layer,
wherein a maximum width or diameter of the post layer is equal to or less than a minimum width or diameter of the barrier layer, and a modulus of elasticity of the second protection layer is greater than a modulus of elasticity of the third protection layer.
17. The semiconductor package of claim 16 , wherein a first surface of the post layer in contact with the barrier layer is a flat surface, and a thickness of the post layer is less than a maximum thickness of the solder layer.
18. The semiconductor package of claim 17 , wherein the post layer has a circular shape in a plan view, and the post layer has a single pillar in which a width or diameter of a lower portion corresponding to a second surface opposite the first surface is greater than a width or diameter of an upper portion corresponding to the first surface.
19. The semiconductor package of claim 16 , wherein the post layer has a single continuous structure of a circular shape or ring shape in a plan view.
20. The semiconductor package of claim 16 , wherein the post layer comprises a plurality of sub-post layers arranged in a circular shape along an edge of the post-exposing hole.