Semiconductor device and semiconductor package

1. A semiconductor device comprising:

a semiconductor layer;

a first switching element and a second switching element commonly formed on the semiconductor layer, the first switching element and the second switching element being alternately arranged;

an interlayer insulating film formed on the semiconductor layer, the first switching element and the second switching element being covered with the interlayer insulating film;

a first output terminal formed on the interlayer insulating film, the first output terminal having a first contact portion electrically connected to the first switching element through the interlayer insulating film such that the first output terminal forms a first end portion of the first switching element;

a second output terminal formed on the interlayer insulating film, the second output terminal having a second contact portion electrically connected to the second switching element through the interlayer insulating film such that the second output terminal forms a first end portion of the second switching element; and

a gate terminal formed on the interlayer insulating film, the gate terminal being commonly electrically connected to the first switching element and the second switching element through the interlayer insulating film, the gate terminal being arranged on a center portion of a first side of the semiconductor layer such that the gate terminal is surrounded by the first contact portion and the second contact portion from three sides other than the first side of the semiconductor layer, wherein

the first contact portion and the second contact portion are alternately arranged,

the first output terminal and the second output terminal are formed into comb shapes to be engaged with each other,

the first output terminal has a plurality of first teeth portions extending in a first direction along the first side of the semiconductor layer, a first connection portion extending in a second direction perpendicular to the first direction and connecting the plurality of the first teeth portions, and a first protruding portion connected to the first connecting portion and protruding toward the gate terminal such that the first protruding portion has a first width in the second direction larger than a width of each of the first teeth portions in the second direction,

the second output terminal has a plurality of second teeth portions extending in the first direction to be engaged with the first teeth portions, a second connection portion extending in the second direction and connecting the plurality of the second teeth portions, and a second protruding portion connected to the second connection portion and protruding toward the gate terminal such that the second protruding portion has a second width in the second direction larger than a width of each of the second teeth portions in the second direction, and

the gate terminal is sandwiched between the first protruding portion and the second protruding portion.

2. The semiconductor device according to claim 1 , wherein

a first side of the gate terminal is adjacent to the first contact portion in the first direction,

a second side of the gate terminal opposite to the first side of the gate terminal is adjacent to the second contact portion in the first direction.

3. The semiconductor device according to claim 1 , further comprising:

linear first unit cell rows, each of which is formed by a plurality of the first switching elements, and

linear second unit cell rows, each of which is formed by a plurality of the second switching elements, wherein

the linear first unit cell rows and the linear second unit cell rows are spaced from each other and alternately arranged.

4. The semiconductor device according to claim 3 , wherein each of the first teeth portions is provided on an upper side of the first unit cell rows and each of the second teeth portions is provided on an upper side of the second unit cell rows.

5. The semiconductor device according to claim 1 , wherein

the first switching element includes a p-channel MISFET, and

the second switching element includes a p-channel MISFET.

6. The semiconductor device according to claim 1 , wherein

a plurality of the first switching elements and a plurality of the second switching elements are arranged in a matrix as a whole, and

the plurality of the first switching elements and the plurality of the second switching elements are alternately arranged respectively in a row direction and a column direction.

7. The semiconductor device according to claim 1 , wherein

the semiconductor layer has a common first conductivity type drain region for the first switching element and the second switching element,

the first switching element includes a first body region of a second conductivity type formed on a surface portion of the semiconductor layer, a first source region of the first conductivity type formed on a surface portion of the first body region, and a first gate electrode facing the first body region,

the second switching element includes a second body region of the second conductivity type formed on the surface portion of the semiconductor layer, a second source region of the first conductivity type formed on a surface portion of the second body region, and a second gate electrode facing the second body region.

8. The semiconductor device according to claim 1 , wherein the semiconductor layer is formed in a square shape in a plan view having a surface, a back surface on the opposite side of the surface, and side surfaces between the surface and the back surface, and

the semiconductor device further comprises:

a surface insulation film formed on the semiconductor layer so as to cover at least the surface of the semiconductor layer;

a first pad of a part of the first output terminal arranged in a central portion of a first peripheral edge portion along one of the side surfaces of the semiconductor layer on the surface side of the semiconductor layer and spaced from both end corner portions of the first peripheral edge portion;

a second pad of a part of the second output terminal arranged in one end corner portion of a second peripheral edge portion facing the first peripheral edge portion of the semiconductor layer; and

a third pad of a part of the gate terminal arranged in an other end corner portion of the second peripheral edge portion of the semiconductor layer.

9. The semiconductor device according to claim 8 , wherein the semiconductor layer includes a semiconductor layer of a rectangular shape in a plan view, and

the first peripheral edge portion and the second peripheral edge portion include peripheral edge portions along the longitudinal direction of the semiconductor layer.

10. The semiconductor device according to claim 9 , wherein

providing that a first arc with a top of the one end corner portion of the second peripheral edge portion as a center and with length of a short side of the semiconductor layer as a radius, and a second arc with a top of the other end corner portion of the second peripheral edge portion as a center and with the length of the short side of the semiconductor layer as a radius are formed on the surface of the semiconductor layer,

the first pad is arranged in a region on the outer side of the first arc and in a region on the outer side of the second arc.

11. The semiconductor device according to claim 10 , wherein

the first arc and the second arc have such size that the arcs cross each other on the semiconductor layer, and

the first pad is formed into a triangle having a pair of tangent lines running from an intersection point between the first arc and the second arc respectively to the first arc and the second arc, the tangent lines serving as two sides of the triangle.

12. The semiconductor device according to claim 10 , wherein the second pad is formed into a fan shape concentric to the first arc.

13. The semiconductor device according to claim 10 , wherein the third pad is formed into a fan shape concentric to the second arc.

14. A semiconductor package comprising:

the semiconductor device according to claim 1 ; and

a sealing resin that seals the whole or part of the semiconductor device.