IP Library › Granted Patent US 11,558,260
Granted Patent B2
US 11,558,260 · App. 16/857,843 · Granted Jan 17, 2023

Network node memory utilization analysis

Inventors: Ramana Rao Kompella (Cupertino, CA); Chandra Nagarajan (Fremont, CA); John Thomas Monk (Palo Alto, CA); Purna Mani Kumar Ghantasala (Sunnyvale, CA)
Assignee: Cisco Technology, Inc.
H04L41/14H04L41/0866H04L41/0893H04L41/145H04L41/22H04L41/24H04L41/0253H04L41/12H04L43/10
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Quick Facts
Patent No.
US 11,558,260
App. No.
16/857,843
Granted
Jan 17, 2023
Kind
B2
Abstract

Systems, methods, and computer-readable media analyzing memory usage in a network node. A network assurance appliance may be configured to query a node in the network fabric for a number of hardware level entries, stored in memory for the node, that are associated with a concrete level network rule. The network assurance appliance may identify a logical level network intent associated with the concrete level network rule, identify a logical level component of the logical level network intent, and attribute the number of hardware level entries to the logical level component.

Claims (46)

1. A computer-implemented method comprising:

determining a hit count for at least one respective rule of a plurality of rules implemented on a leaf node, wherein the hit count is indicative of a number of times the at least one respective rule of the plurality of rules is triggered;

identifying one or more logical-level components of a logical model as being associated with one or more rules of the plurality of rules;

attributing the hit count for the at least one respective rule of the plurality of rules to an identified logical-level component of the logical model; and

generating a report specifying at least one relationship between the one or more logical-level components of the logical model and the hit count for the at least one respective rule of the plurality of rules.

2. The computer-implemented method of claim 1 , further comprising:

receiving a query for a total number of hardware level entries associated with a selected component of the one or more components; and

providing the total number of hardware level entries in response to the query.

3. The computer-implemented method of claim 1 , further comprising:

generating a mapping of a total number of hardware level entries to the one or more components for logical level network intents implemented on the leaf node based on a number of hardware level entries attributed to the one or more components; and

providing the total number of hardware level entries to an interface.

4. The computer-implemented method of claim 1 , further comprising:

receiving, from the leaf node, the plurality of rules implemented on the leaf node.

5. The computer-implemented method of claim 4 , further comprising:

querying the leaf node for the plurality of rules implemented on the leaf node.

6. The computer-implemented method of claim 4 , wherein the plurality of rules implemented on the leaf node received from the leaf node comprises zoning rule mapping information.

7. The computer-implemented method of claim 1 , wherein a memory for the leaf node is a Ternary Content-Addressable Memory.

8. The computer-implemented method of claim 1 , wherein the one or more components comprise at least one of a contract, an endpoint, an endpoint group, a bridge domain, or a protocol.

9. The computer-implemented method of claim 1 , wherein the plurality of rules include an access control rule.

10. A system comprising:

one or more processors; and

at least one computer-readable storage medium storing instructions which, when executed by the one or more processors, cause the system to:

determine a hit count for at least one respective rule of a plurality of rules implemented on a leaf node, wherein the hit count is indicative of a number of times the at least one respective rule of the plurality of rules is triggered;

identify one or more logical-level components of a logical model as being associated with one or more rules of the plurality of rules;

attribute the hit count for the least one respective rule of the plurality of rules to an identified logical-level component of the logical model; and

generate a report specifying at least one relationship between the one or more logical-level components of the logical model and the hit count for the at least one respective rule of the plurality of rules.

11. The system of claim 10 , wherein the leaf node is in a network fabric.

12. The system of claim 10 , comprising further instructions which when executed by the one or more processors, cause the system to:

process a query for hardware level entries associated with the one or more components by providing the hardware level entries to an interface in response to the query.

13. The system of claim 10 , comprising further instructions which when executed by the one or more processors, cause the system to:

generate a mapping of a total number of hardware level entries to the one or more components for logical level network intents implemented on the leaf node based on a number of hardware level entries attributed to the one or more components; and

provide the total number of hardware level entries to an interface.

14. The system of claim 13 , wherein the interface is a web interface configured to provide status information for a network fabric to a network administrator.

15. At least one non-transitory computer-readable medium comprising instructions, which when executed by one or more processors, cause the one or more processors to:

determine a hit count for at least one respective rule of a plurality of rules implemented on a leaf node, wherein the hit count is indicative of a number of times the at least one respective rule of the plurality of rules is triggered;

identify one or more logical-level components of a logical model as being associated with one or more rules of the plurality of rules;

attribute the hit count for the at least one respective rule of the plurality of rules to an identified logical-level component of the logical model; and

generate a report specifying at least one relationship between the one or more logical-level components of the logical model and the hit count for the at least one respective rule of the plurality of rules.

16. The at least one non-transitory computer-readable medium of claim 15 , comprising further instructions, which when executed by the one or more processors, cause the one or more processors to:

provide a total number of hardware level entries to a network administrator.

17. The at least one non-transitory computer-readable medium of claim 16 , comprising further instructions, which when executed by the one or more processors, cause the one or more processors to:

process a query for a total number of hardware level entries by providing the total number of hardware level entries in response to the query.

18. The at least one non-transitory computer-readable medium of claim 15 , comprising further instructions, which when executed by the one or more processors, cause the one or more processors to:

receive, from the leaf node, the plurality of rules implemented on the leaf node.

19. The at least one non-transitory computer-readable medium of claim 15 , wherein a number of hardware level entries comprises at least one Ternary Content-Addressable Memory entry.

20. The at least one non-transitory computer-readable medium of claim 15 , wherein the one or more components comprise at least one of a contract, an endpoint, an endpoint group, a bridge domain, or a protocol.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 24, 2020
From: KOMPELLA, RAMANA RAO; NAGARAJAN, CHANDRA; MONK, JOHN THOMAS; GHANTASALA, PURNA MANI KUMAR
To: CISCO TECHNOLOGY, INC.
Reel/Frame 052490/0201 →
Continuity (3)
Continuation 15661912 · Jul 27, 2017
Provisional Application 62521638 · Jun 19, 2017
Related Publication 20200252297A1 · Aug 6, 2020