Graphics systems and methods for accelerating synchronization using fine grain dependency check and scheduling optimizations based on available shared memory space

1. A graphics multiprocessor, comprising:

a plurality of processing resources; and

synchronization circuitry that is configured to determine availability of at least one processing resource and when at least one processing resource is available, to perform a fine grain dependency check of availability of a minimum data size of data of a first matrix and a minimum data size of data of a second matrix in shared memory or cache to start a computation before a complete data set for the computation is available.

2. The graphics multiprocessor of claim 1 , further comprising:

a plurality of registers, wherein the synchronization circuitry is further configured to cause the loading of the minimum data size of the data of the first matrix including dependent data or operands into registers if the dependent data or operands are available in the shared local memory or cache.

3. The graphics multiprocessor of claim 2 , wherein the synchronization circuitry is further configured to cause the loading of the dependent data or operands from the registers into an available processing resource for execution.

4. The graphics multiprocessor of claim 3 , wherein the dependent data or operands are loaded into tile registers.

5. The graphics multiprocessor of claim 1 , wherein the fine grain dependency check of availability of the minimum data size of the data of the first matrix and the minimum data size of the data of the second matrix in shared local memory or cache comprises a dependency check for the minimum data size of the data of the first matrix including a row of the first matrix and the minimum data size of the data of the second matrix including a column of the second matrix needed for a computation.

6. A method for accelerated synchronization operations using fine grain dependency check of a graphics processing unit (GPU), comprising:

determining, with a synchronization circuitry of the GPU, availability of at least one processing resource; and

given availability of at least one processing resource, performing with the synchronization circuitry a fine grain dependency check of availability of a row of data of a first matrix and a column of data of a second matrix in shared memory or cache to start a computation before a complete data set for the computation is available.

7. The method of claim 6 , further comprising:

if the row of the data of the first matrix or the column of the data of the second matrix is available in the shared memory or cache, loading with the synchronization circuitry, the row of the data of the first matrix or the column of the data of the second matrix into a register file.

8. The method of claim 7 , further comprising:

loading the row of the data of the first matrix or the column of the data of the second matrix from the register file into an available processing resource or processing engine for execution.

9. The method of claim 8 , wherein the row of the data of the first matrix or the column of the data of the second matrix is loaded into a tile register.

10. The method of claim 6 , wherein the fine grain dependency check of availability of the row of the data of the first matrix or the column of the data of the second matrix in shared local memory or cache comprises a dependency check for a minimum data size needed for a computation.

11. A system, comprising:

shared memory or cache memory to store data;

a plurality of processing resources; and

circuitry coupled to the shared memory or cache memory, the circuitry is configured to determine availability of at least one processing resource and when at least one processing resource is available, to perform a fine grain dependency check of availability of a minimum data size of data of a first matrix and a minimum data size of data of a second matrix in the shared memory or the cache memory to start a computation before a complete data set for the computation is available.

12. The system of claim 11 , further comprising:

a system memory or graphics memory coupled to the shared memory or the cache memory; and

a plurality of registers, wherein the circuitry is further configured to cause the loading of the minimum data size of the data of the first matrix including dependent data or operands into a register of the plurality of registers if the dependent data or operands are available in the shared local memory or the cache memory.

13. The system of claim 12 , wherein the circuitry is further configured to cause the loading of the dependent data or operands from the register into an available processing resource for execution.

14. The system of claim 13 , wherein the dependent data or operands are loaded into tile registers.

15. The system of claim 11 , wherein the fine grain dependency check of availability of the minimum data size of the data of the first matrix and the minimum data size of the data of the second matrix in the shared local memory or the cache memory comprises a dependency check for the minimum data size of the data of the first matrix including a row of the first matrix and the minimum data size of the data of the second matrix including a column of the second matrix needed for a computation.

16. A machine-readable storage medium comprising executable instructions which when executed by a processor of a graphics processing unit (GPU) cause the processor to perform a method for accelerated synchronization operations using fine grain dependency check, the method comprising:

determining availability of at least one processing resource; and

given availability of at least one processing resource, performing a fine grain dependency check of availability of a row of data of a first matrix and a column of data of a second matrix in shared memory or cache memory to start a computation before a complete data set for the computation is available.

17. The machine-readable storage medium of claim 16 , the method further comprising:

if the row of the data of the first matrix or the column of the data of the second matrix is available in the shared memory or the cache memory, loading the row of the data of the first matrix or the column of the data of the second matrix into a register file.

18. The machine-readable storage medium of claim 17 , the method further comprising:

loading the row of the data of the first matrix or the column of the data of the second matrix from the register file into an available processing resource or processing engine for execution.

19. The machine-readable storage medium of claim 18 , wherein the row of the data of the first matrix or the column of the data of the second matrix is loaded into a tile register.

20. The machine-readable storage medium of claim 16 , wherein the fine grain dependency check of availability of the row of the data of the first matrix or the column of the data of the second matrix in the shared memory or the cache memory comprises a dependency check for a minimum data size needed for a computation.