Fixed voltage sensing in a memory device

1. An apparatus comprising:

a ferroelectric random-access memory (FeRAM) circuit comprising:

a ferroelectric memory cell coupled to a data line; and

a reference capacitance coupled to a reference line; and

first and second precharge transistors coupled between the data line and the reference line,

wherein the ferroelectric memory cell, the reference capacitance, and the first and second precharge transistors each include a first node directly coupled to a plate node, and

wherein voltages of the first nodes of the ferroelectric memory cell, the reference capacitance, and the first and second precharge transistors are equal to each other throughout different operations of the FeRAM circuit.

2. The apparatus of claim 1 , wherein the first and second precharge transistors are configured to selectively precharge the data line and the reference line to a voltage of the plate node.

3. The apparatus of claim 1 , wherein the different operations of the FeRAM circuit comprise sense and write operations of the ferroelectric memory cell, and

wherein the plate node is held at a first fixed voltage during the sense operation of the ferroelectric memory cell and at a second fixed voltage during the write operation of the ferroelectric memory cell.

4. The apparatus of claim 3 , wherein the first fixed voltage is a ground voltage and the second fixed voltage is a voltage higher than the first fixed voltage.

5. The apparatus of claim 1 , wherein the ferroelectric memory cell comprises first and second nodes, the first node coupled to the plate node and the second node coupled to the data line through a first access transistor,

wherein the reference capacitance comprises first and second nodes, the first node coupled to the plate node and the second node coupled to the reference line through a second access transistor,

wherein the first and second precharge transistors are coupled in series between the data line and the reference line, and

wherein the first and second precharge transistors each comprise first and second nodes, the first nodes coupled to the plate node, the second node of the first precharge transistor coupled to the data line, and the second node of the second precharge transistor coupled to the reference line.

6. The apparatus of claim 1 , comprising:

first and second pull up transistors having respective control gates coupled to the reference line,

wherein the first and second pull up transistors are configured to mirror displacement current from the reference line to the data line.

7. The apparatus of claim 1 , wherein the reference capacitance comprises a reference memory cell.

8. The apparatus of claim 1 , wherein the reference capacitance comprises a reference capacitor.

9. The apparatus of claim 1 , comprising:

an equilibrate transistor, separate from the first and second precharge transistors, the equilibrate transistor coupled between the data line and the reference line and having a control gate configured to receive an equilibrate signal and to selectively mirror displacement current from the reference line to the data line.

10. A system comprising:

a controller to control the system;

a ferroelectric random-access memory (FeRAM) circuit comprising:

a ferroelectric memory cell coupled to a data line; and

a reference capacitance coupled to a reference line; and

first and second precharge transistors coupled between the data line and the reference line,

wherein the ferroelectric memory cell, the reference capacitance, and the first and second precharge transistors each include a first node directly coupled to a plate node,

wherein voltages of the first nodes of the ferroelectric memory cell, the reference capacitance, and the first and second precharge transistors are equal to each other throughout different operations of the FeRAM circuit,

wherein the different operations of the FeRAM circuit comprise sense and write operations of the ferroelectric memory cell, and

wherein the controller is configured to hold the plate node at a first fixed voltage during the sense operation of the ferroelectric memory cell and at a second fixed voltage during the write operation of the ferroelectric memory cell.

11. The system of claim 10 , wherein the controller is configured to selectively provide a control signal to the first and second precharge transistors to selectively precharge the data line and the reference line to a voltage of the plate node.

12. The system of claim 10 , wherein the ferroelectric memory cell comprises first and second nodes, the first node coupled to the plate node and the second node coupled to the data line through a first access transistor,

wherein the reference capacitance comprises first and second nodes, the first node coupled to the plate node and the second node coupled to the reference line through a second access transistor,

wherein the first and second precharge transistors are coupled in series between the data line and the reference line, and

wherein the first and second precharge transistors each comprise first and second nodes, the first nodes coupled to the plate node, the second node of the first precharge transistor coupled to the data line, and the second node of the second precharge transistor coupled to the reference line.

13. The system of claim 10 , comprising:

first and second pull up transistors having respective control gates coupled to the reference line,

wherein the first and second pull up transistors are configured to mirror displacement current from the reference line to the data line.

14. The system of claim 10 , wherein the reference capacitance comprises at least one of a reference memory cell or a reference capacitor.

15. The system of claim 10 , comprising:

an equilibrate transistor, separate from the first and second precharge transistors, the equilibrate transistor coupled between the data line and the reference line and having a control gate configured to receive an equilibrate signal and to selectively mirror displacement current from the reference line to the data line.

16. A method comprising:

holding voltages of first nodes of first and second precharge transistors, a ferroelectric memory cell, and a reference capacitance of a ferroelectric random-access memory (FeRAM) circuit equal to each other, using a plate node, throughout different operations of the FeRAM circuit, and

wherein the ferroelectric memory cell is coupled to a data line, the reference capacitance is coupled to a reference line, and the first and second precharge transistors are coupled between the data line and the reference line.

17. The method of claim 16 , comprising:

selectively precharging the data line and the reference line to a voltage of the plate node using the first and second precharge transistors.

18. The method of claim 16 , wherein holding the first nodes of the first and second precharge transistors, the ferroelectric memory cell, and the reference capacitance at the same potential throughout the different operations of the FeRAM circuit comprise:

holding the first nodes of the first and second precharge transistors, the ferroelectric memory cell, and the reference capacitance at a first fixed voltage during the sense operation of the ferroelectric memory cell; and

holding the first nodes of the first and second precharge transistors, the ferroelectric memory cell, and the reference capacitance at a second fixed voltage during the write operation of the ferroelectric memory cell.

19. The method of claim 16 , wherein the ferroelectric memory cell comprises first and second nodes, the first node coupled to the plate node and the second node coupled to the data line through a first access transistor,

wherein the reference capacitance comprises first and second nodes, the first node coupled to the plate node and the second node coupled to the reference line through a second access transistor,

wherein the first and second precharge transistors are coupled in series between the data line and the reference line, and

wherein the first and second precharge transistors each comprise first and second nodes, the first nodes coupled to the plate node, the second node of the first precharge transistor coupled to the data line, and the second node of the second precharge transistor coupled to the reference line.

20. The method of claim 16 , wherein the reference capacitance comprises at least one of a reference memory cell or a reference capacitor.