3D stackable bidirectional access device for memory array
A method of manufacturing a vertical metal-semiconductor field-effect transistor (MESFET) device is provided. The method includes forming a first oxide layer, forming a first electrode in the oxide layer, forming a crystallized silicon layer on the first electrode, forming a second electrode on the first oxide layer and on sidewalls of the crystalized silicon layer, forming a second oxide layer on upper surfaces of the second electrode. The method also includes forming a third electrode on an upper surface of the crystallized silicon layer.
1. A method of manufacturing a vertical metal-semiconductor field-effect transistor (MESFET) device, the method comprising:
forming a first oxide layer;
forming a first electrode in the first oxide layer;
forming a crystallized silicon layer directly contacting the first electrode;
forming a second electrode on the first oxide layer and on sidewalls of the crystallized silicon layer;
forming a second oxide layer on upper surfaces of the second electrode; and
forming a third electrode on an upper surface of the crystallized silicon layer.
2. The method according to claim 1 , wherein the first electrode is a source electrode, the second electrode is a gate electrode, and the third electrode is a drain electrode.
3. The method according to claim 1 , wherein at least a portion of the second oxide layer is formed between the second electrode and the third electrode.
4. The method according to claim 1 , wherein forming the crystallized silicon layer includes laser annealing the crystallized silicon layer.
5. The method according to claim 1 , wherein the vertical MESFET device is formed on a BEOL layer of a semiconductor device.
6. The method according to claim 1 , wherein a width of the crystallized silicon layer is wider than a width of the first electrode.
7. The method according to claim 1 , wherein forming the crystallized silicon layer includes doping with at least one material selected from the group consisting of arsenic (As), antimony (Sb), boron (B), and phosphorus (P).
8. A vertical MESFET device comprising:
a first oxide layer;
a first electrode formed in the first oxide layer;
a crystallized silicon layer directly contacting the first electrode;
a second electrode formed on the first oxide layer and on sidewalls of the crystallized silicon layer;
a second oxide layer formed on upper surfaces of the second electrode; and
a third electrode formed on an upper surface of the crystallized silicon layer.
9. The device according to claim 8 , wherein the first electrode is a source electrode, the second electrode is a gate electrode, and the third electrode is a drain electrode.
10. The device according to claim 8 , wherein at least a portion of the second oxide layer is formed between the second electrode and the third electrode.
11. The device according to claim 8 , wherein forming the crystallized silicon layer includes laser annealing the crystallized silicon layer.
12. The device according to claim 8 , wherein the vertical MESFET device is formed on a BEOL layer of a semiconductor device.
13. The device according to claim 8 , wherein a width of the crystallized silicon layer is wider than a width of the first electrode.
14. The device according to claim 8 , wherein the crystallized silicon layer is doped with at least one material selected from the group consisting of arsenic (As), antimony (Sb), boron (B), and phosphorus (P).
15. A semiconductor device comprising:
a bidirectional access device that is a vertical MESFET device, the bidirectional access device including
a first oxide layer,
a first electrode formed in the first oxide layer,
a crystallized silicon layer directly contacting the first electrode,
a second electrode formed on the first oxide layer and on sidewalls of the crystallized silicon layer,
a second oxide layer formed on upper surfaces of the second electrode, and
a third electrode formed on an upper surface of the crystallized silicon layer; and
a memory device connected to the bidirectional access device.
16. The semiconductor device according to claim 15 , wherein the memory device is phase change memory (PCM) device.
17. The semiconductor device according to claim 15 , wherein the memory device is a resistive random access memory (RRAM) device.
18. The semiconductor device according to claim 15 , further comprising a plurality of vertical MESFET devices and memory devices three-dimensionally stacked in a vertical direction of the semiconductor device.
19. The semiconductor device according to claim 15 , wherein a width of the crystallized silicon layer is wider than a width of the first electrode.