Cell having stacked pick-up region

1. An integrated circuit comprising:

two parallel active zones extending in a first direction that includes a p-type active zone located in an n-type well and an n-type active zone located in a p-type well, wherein each of the p-type active zone and the n-type active zone includes a channel region between a source or a drain aligned along the first direction, and wherein the p-type active zone having channel regions is separated from the n-type active zone having channel regions along a second direction that is different from the first direction;

an n-type pick-up region located in the n-type well;

a p-type pick-up region located in the p-type well;

wherein the n-type pick-up region and the p-type pick-up region are separated from each other along the second direction;

a first power rail extending in the first direction and conductively connected with the n-type pick-up region, and wherein the p-type active zone is between the first power rail and the n-type active zone and separates the first power rail from the n-type active zone;

wherein the n-type pick-up region has an n-type dopant concentration which is higher than an n-type dopant concentration of the n-type well, and the n-type pick-up region is configured to connect the n-type well conductively to a first supply voltage on the first power rail;

a first conductive segment extending in the second direction and in conductive contact with the n-type pick-up region;

a first via connection connected between the first power rail and the first conductive segment;

a second power rail extending in the first direction and conductively connected with the p-type pick-up region, and wherein the n-type active zone is between the second power rail from the p-type active zone and separates the second power rail from the p-type active zone;

wherein the p-type pick-up region has a p-type dopant concentration which is higher than a p-type dopant concentration of the p-type well, and the p-type pick-up region is configured to connect the p-type well conductively to a second supply voltage on the second power rail;

a second conductive segment extending in the second direction and in conductive contact with the p-type pick-up region; and

a second via connection connected between the second power rail and the second conductive segment.

2. The integrated circuit of claim 1 , wherein the n-type pick-up region is between the first power rail and the p-type active zone and separates the first power rail from the p-type active zone.

3. The integrated circuit of claim 1 , wherein the p-type pick-up region is between the second power rail and the n-type active zone and separates the second power rail from the n-type active zone.

4. The integrated circuit of claim 1 , wherein the n-type pick-up region is separated from the p-type pick-up region by the two parallel active zones.

5. The integrated circuit of claim 1 , wherein the two parallel active zones are separated in by the n-type pick-up region and the p-type pick-up region.

6. The integrated circuit of claim 1 , wherein an n-type carrier density in the n-type pick-up region is higher than the n-type carrier density in the n-type well, and a p-type carrier density in the p-type pick-up region is higher than the p-type carrier density in the p-type well.

7. The integrated circuit of claim 1 , wherein the n-type pick-up region has a width extending in the first direction and has a height extending in the second direction, and wherein the height is less than 25% of the width.

8. The integrated circuit of claim 1 , wherein the p-type pick-up region has a width extending in the first direction and has a height extending in the second direction, and wherein the height is less than 25% of the width.

9. The integrated circuit of claim 1 , wherein the p-type well is a part of a p-type substrate and the n-type well is formed in the p-type substrate.

10. The integrated circuit of claim 1 , wherein the n-type well is a part of a n-type substrate and the p-type well is formed in the n-type substrate.

11. The integrated circuit of claim 1 , further comprising:

an analog cell including a circuit having transistors in the p-type active zone and the n-type active zone.

12. An integrated circuit comprising:

two parallel active zones extending in a first direction that includes a first-type active zone in a second-type well and a second-type active zone in a first-type well, wherein each of the first-type active zone and the second-type active zone includes a channel region between a source or a drain aligned along the first direction, and wherein the first-type active zone having channel regions is separated from the second-type active zone having channel regions along a second direction that is perpendicular to the first direction;

a first power rail extending in the first direction and configured to have a first voltage, and wherein the first-type active zone is between the first power rail and the second-type active zone and separates the first power rail from the second-type active zone;

a second power rail extending in the first direction and configured to have a second voltage, and wherein the second-type active zone is between the second power rail from the first-type active zone and separates the second power rail from the first-type active zone;

two parallel cell boundaries extending in the second direction;

a first-type pick-up region, in the first-type well and between the two parallel cell boundaries, conductively connected with the first power rail;

wherein the first-type pick-up region has a first-type dopant concentration which is higher than a first-type dopant concentration of the first-type well, and the first-type pick-up region is configured to connect the first-type well conductively to the first voltage on the first power rail;

a first conductive segment extending in the second direction and in conductive contact with the first-type pick-up region;

a first via connection connected between the first power rail and the first conductive segment; and

wherein the first-type pick-up region is separated from the two parallel active zones along a direction that is different from the first direction.

13. The integrated circuit of claim 12 , further comprising:

a second-type pick-up region, in the second-type well and between the two parallel cell boundaries, conductively connected to the second power rail;

a second conductive segment extending in the second direction and in conductive contact with the second-type pick-up region; and

a second via connection connected between the second power rail and the second conductive segment.

14. The integrated circuit of claim 12 , wherein the first-type well is n-type and the second-type well is p-type, and wherein the first voltage is a first supply voltage and the second voltage is a second supply voltage is lower than the first supply voltage.

15. The integrated circuit of claim 12 , wherein the first-type well is p-type and the second-type well is n-type, and wherein the second voltage is a first supply voltage and the first voltage is a second supply voltage is lower than the first supply voltage.

16. The integrated circuit of claim 12 , further comprising:

an analog cell including a circuit having transistors in the first-type active zone and the second-type active zone.

17. An integrated circuit comprising:

two parallel active zones extending in a first direction that includes a p-type active zone located in an n-type well and an n-type active zone located in a p-type well, wherein each of the p-type active zone and the n-type active zone includes a channel region between a source or a drain aligned along the first direction, and wherein the p-type active zone having channel regions is separated from the n-type active zone having channel regions along a second direction that is different from the first direction;

an n-type pick-up region, in the n-type well, forming a first guard-ring surrounding the p-type active zone;

a p-type pick-up region, in the p-type well, forming a second guard-ring surrounding the n-type active zone;

wherein the n-type pick-up region and the p-type pick-up region are separated from each other along the second direction;

a first power rail extending in the first direction and conductively connected with the n-type pick-up region, and wherein the p-type active zone is between the first power rail and the n-type active zone and separates the first power rail from the n-type active zone;

wherein the n-type pick-up region has an n-type dopant concentration which is higher than an n-type dopant concentration of the n-type well, and the n-type pick-up region is configured to connect the n-type well conductively to a first supply voltage on the first power rail;

a first conductive segment extending in the second direction and in conductive contact with the n-type pick-up region;

a first via connection connected between the first power rail and the first conductive segment;

a second power rail extending in the first direction and conductively connected with the p-type pick-up region, and wherein the n-type active zone is between the second power rail from the p-type active zone and separates the second power rail from the p-type active zone;

wherein the p-type pick-up region has an p-type dopant concentration which is higher than an p-type dopant concentration of the p-type well, and the p-type pick-up region is configured to connect the p-type well conductively to a second supply voltage on the second power rail;

a second conductive segment extending in the second direction and in conductive contact with the p-type pick-up region; and

a second via connection connected between the second power rail and the second conductive segment.

18. The integrated circuit of claim 17 , wherein the n-type pick-up region is configured to have a first supply voltage, and the p-type pick-up region is configured to have a second supply voltage which is lower than the first supply voltage.

19. The integrated circuit of claim 17 , wherein the p-type well is a part of a p-type substrate and the n-type well is formed in the p-type substrate.

20. The integrated circuit of claim 17 , wherein the n-type well is a part of an n-type substrate and the p-type well is formed in the n-type substrate.