IP Library › Granted Patent US 11,563,002
Granted Patent B2
US 11,563,002 · App. 16/418,366 · Granted Jan 24, 2023

Semiconductor devices having gate electrodes and methods of manufacturing the same

Inventors: Jin Woo Kim (Hwaseong-si, KR); Choelhwyi Bae (Hwaseong-si, KR); Yang Gyeom Kim (Hwaseong-si, KR); Sung Eun Kim (Hwaseong-si, KR); Sang Woo Pae (Hwaseong-si, KR); Hyun Chui Sagong (Hwaseong-si, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
H01L27/0922H01L21/28088H01L21/765H01L21/823821H01L21/823842H01L27/0924H01L27/1104H01L29/402H01L29/4966
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Quick Facts
Patent No.
US 11,563,002
App. No.
16/418,366
Granted
Jan 24, 2023
Kind
B2
Abstract

A semiconductor device includes a first fin that protrudes from a substrate and extends in a first direction, a second fin that protrudes from the substrate and extends in the first direction, the first fin and the second fin being spaced apart, a gate line including a dummy gate electrode and a gate electrode, the dummy gate electrode at least partially covering the first fin, the gate electrode at least partially covering the second fin, the dummy gate electrode including different materials from the gate electrode, the gate line covering the first fin and the second fin, the gate line extending in a second direction different from the first direction, and a gate dielectric layer between the gate electrode and the second fin.

Claims (53)

1. A semiconductor device comprising:

a first fin that protrudes from a substrate and extends in a first direction;

a second fin that protrudes from the substrate and extends in the first direction, the first fin and the second fin being spaced apart;

a gate line including a dummy gate electrode and a gate electrode, the dummy gate electrode at least partially covering the first fin, the gate electrode at least partially covering the second fin, the dummy gate electrode including different materials from the gate electrode, the gate line covering the first fin and the second fin, the gate line extending in a second direction different from the first direction, and the dummy gate electrode being included in a same transitor; and

a gate dielectric layer between the gate electrode and the second fin,

wherein the gate electrode extends continuously from the dummy gate electrode so that the gate electrode and the dummy gate electrode are formed over common line of extent.

2. The semiconductor device of claim 1 , wherein a side surface of the dummy gate electrode with respect to the first direction is between the first fin and the second fin.

3. The semiconductor device of claim 1 , wherein

a side surface of the dummy gate electrode with respect to the first direction is above the first fin,

the dummy gate electrode covers a first side surface of the first fin, and

the gate electrode covers the second fin and a second side surface of the first fin.

4. The semiconductor device of claim 1 , wherein

a side surface of the dummy gate electrode with respect to the first direction is above the first fin,

the dummy gate electrode covers a first side surface of the first fin, and

the gate electrode covers the dummy gate electrode, a second side surface of the first fin, and the second fin.

5. The semiconductor device of claim 1 , wherein

an upper surface of the dummy gate electrode is at a lower level than an upper end of the first fin,

the dummy gate electrode covers a first part of a first side surface of the first fin, and

the gate electrode covers the dummy gate electrode, an upper surface of the first fin, a second side surface of the first fin, and the second fin.

6. The semiconductor device of claim 1 , wherein a width of the dummy gate electrode in the first direction is wider than a width of the gate electrode in the first direction.

7. The semiconductor device of claim 1 , wherein a lower surface of the dummy gate electrode is at a lower level than a lower surface of the gate electrode.

8. The semiconductor device of claim 1 , further comprising:

a dummy gate insulating layer between the first fin and the dummy gate electrode.

9. The semiconductor device of claim 1 , wherein the gate dielectric layer covers a side surface of the dummy gate electrode with respect to the first direction.

10. The semiconductor device of claim 9 , wherein the gate dielectric layer extends in the second direction.

11. The semiconductor device of claim 1 , further comprising:

a gate oxide layer between a side surface of the dummy gate electrode with respect to the first direction and the gate dielectric layer.

12. The semiconductor device of claim 11 , further comprising:

a work function adjusting layer on the gate dielectric layer, the second fin and the side surface of the dummy gate electrode.

13. The semiconductor device of claim 11 , wherein

the dummy gate electrode includes a metal, and

the gate dielectric layer covers the side surface of the dummy gate electrode.

14. A semiconductor device comprising:

a first fin that protrudes from a substrate and extends in a first direction;

a second fin that protrudes from the substrate and extends in the first direction;

a third fin that protrudes from the substrate and extends in the first direction, the first fin, the second fin and the third fin being spaced apart;

a gate line including a dummy gate electrode, a first gate electrode and a second gate electrode, the dummy gate electrode covering the first fin, the first gate electrode covering the second fin, the second gate electrode covering the third fin, the dummy gate electrode including different materials from the first gate electrode and the second gate electrode, the gate line extending in a second direction different from the first direction;

a first gate dielectric layer between the first gate electrode and the second fin; and

a second gate dielectric layer between the second gate electrode and the third fin,

wherein the first and second gate electrodes extend continuously from the dummy gate electrode so that the first and second gate electrodes and the dummy gate electrode are formed over common line of extent.

15. The semiconductor device of claim 14 , wherein the first gate electrode and the second gate electrode include different materials.

16. The semiconductor device of claim 14 , further comprising:

a first work function adjusting layer between the first gate electrode and the first gate dielectric layer; and

a second work function adjusting layer between the second gate electrode and the second gate dielectric layer, the first work function adjusting layer and the second work function adjusting layer including different materials.

17. The semiconductor device of claim 14 , wherein the first gate dielectric layer covers a side surface of the dummy gate electrode with respect to the first direction.

18. The semiconductor device of claim 17 , further comprising:

a gate oxide layer between the first gate dielectric layer and the side surface of the dummy gate electrode.

19. The semiconductor device of claim 14 , wherein the second gate dielectric layer covers a side surface of the first gate electrode with respect to the first direction.

20. A semiconductor device comprising:

a fin that protrudes from a substrate and extends in a first direction;

a gate line including a dummy gate electrode and a gate electrode, the dummy gate electrode covering a first side surface of the fin, the gate electrode covering a second side surface of the fin, the dummy gate electrode including different materials from the gate electrode, the gate line covering the fin and extending in a second direction different from the first direction;

a dummy gate insulating layer between the dummy gate electrode and the fin; and

a gate dielectric layer between the gate electrode and the fin.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 22, 2019
From: KIM, JIN WOO; BAE, CHOELHWYI; KIM, YANG GYEOM; KIM, SUNG EUN; PAE, SANG WOO; SAGONG, HYUN CHUL
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 049254/0577 →
Priority Claims (1)
KR 10-2018-0154900 · Dec 5, 2018 · national
Continuity (1)
Related Publication 20200185383A1 · Jun 11, 2020