Memory arrays and methods used in forming a memory array comprising strings of memory cells

1. A memory array comprising strings of memory cells, comprising:

laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers, operative channel-material strings of memory cells extending through the insulative tiers and the conductive tiers in a memory-array region;

the insulative tiers and the conductive tiers of the laterally-spaced memory blocks extending from the memory-array region into a stair-step region that is adjacent the memory-array region, the insulative tiers and the conductive tiers of the memory blocks in the stair-step region comprising operative stair-step structures that are laterally-spaced relative one another by trenches that extend vertically through multiple of the insulative tiers and conductive tiers, the operative stair-step structures and the trenches each being individually horizontally-longitudinally-elongated;

individual of the stair-step structures comprising a pair of elevationally-extending walls that are spaced laterally-inward from sides of the respective stair-step structure, that are laterally-spaced relative one another, and that are individually horizontally-longitudinally-elongated; and

the individual stair-step structures having operative through-array-vias (TAV's) along the trenches and being devoid of operative TAV's laterally-between the pair of walls.

2. The memory array of claim 1 wherein the individual stair-step structures comprise a landing region and a step region comprising steps that is adjacent the landing region, at least a portion of the walls being in the landing region.

3. The memory array of claim 1 wherein the individual stair-step structures comprise a landing region and a step region comprising steps that is adjacent the landing region, at least a portion of the walls being in the step region.

4. The memory array of claim 1 wherein the individual stair-step structures comprise a landing region and a step region comprising steps that is adjacent the landing region, the walls being in each of the landing region and the step region.

5. The memory array of claim 1 comprising more elevationally-extending walls that connect with the pair of walls, the pair of walls and the more walls collectively completely-encircling an island that includes space between the laterally-spaced walls of the pair of walls.

6. The memory array of claim 5 wherein the island is longitudinally-elongated along the pair of walls.

7. The memory array of claim 1 wherein the walls are horizontally parallel relative one another.

8. The memory array of claim 1 wherein at least one of the walls is horizontally parallel horizontal-longitudinal-orientation of the stair-step structure it is in.

9. The memory array of claim 1 wherein at least one of the walls is not horizontally parallel horizontal-longitudinal-orientation of the stair-step structure it is in.

10. The memory array of claim 1 wherein at least one of the walls is vertical or within 10° of vertical.

11. The memory array of claim 1 wherein at least one of the walls is horizontally straight-linear.

12. The memory array of claim 1 comprising NAND.

13. A memory array comprising strings of memory cells, comprising:

laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers, operative channel-material strings of memory cells extending through the insulative tiers and the conductive tiers in a memory-array region;

the insulative tiers and the conductive tiers of the laterally-spaced memory blocks extending from the memory-array region into a stair-step region that is adjacent the memory-array region, the insulative tiers and the conductive tiers of the memory blocks in the stair-step region comprising operative stair-step structures that are laterally-spaced relative one another by trenches that extend vertically through multiple of the insulative tiers and conductive tiers; the operative stair-step structures and the trenches each being individually horizontally-longitudinally-elongated; and

individual of the stair-step structures comprising a pair of elevationally-extending walls that are spaced laterally-inward from sides of the respective stair-step structure, that are laterally-spaced relative one another, and that are individually horizontally-longitudinally-elongated; at least one of the walls neither being horizontally parallel horizontal-longitudinal-orientation of its individual stair-step structure nor angled orthogonally relative said horizontal-longitudinal-orientation.

14. A memory array comprising strings of memory cells, comprising:

laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers, operative channel-material strings of memory cells extending through the insulative tiers and the conductive tiers, the operative channel-material strings in the laterally-spaced memory blocks comprising part of a memory plane; and

an elevationally-extending wall of material extending vertically through multiple of the alternating insulative tiers and conductive tiers in the memory plane laterally-between immediately-laterally-adjacent of the memory blocks and that completely encircles an island that is laterally-between immediately-laterally-adjacent of the memory blocks in the memory plane.

15. A memory array comprising strings of memory cells, comprising:

laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers, operative channel-material strings of memory cells extending through the insulative tiers and the conductive tiers, the operative channel-material strings in the laterally-spaced memory blocks comprising part of a memory plane; and

a pair of elevationally-extending walls of material extending vertically through multiple of the alternating insulative tiers and conductive tiers in the memory plane laterally-between immediately-laterally-adjacent of the memory blocks, that are laterally-spaced relative one another, and that are individually horizontally-longitudinally-elongated; at least one of the walls not being horizontally parallel horizontal-longitudinal-orientation of the immediately-laterally-adjacent memory blocks which the at least one of the walls is laterally-there-between.

16. A memory array comprising strings of memory cells, comprising:

laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers, operative channel-material strings of memory cells extending through the insulative tiers and the conductive tiers, the operative channel-material strings in the laterally-spaced memory blocks comprising part of a memory plane; and

a pair of elevationally-extending walls of material extending elevationally through multiple of the alternating insulative tiers and conductive tiers, the elevationally extending walls being laterally-spaced relative one another and that are individually horizontally-longitudinally-elongated, the pair of walls being edge-of-plane.

17. The memory array of claim 16 comprising more elevationally-extending walls that are edge-of-plane and connect with the pair of walls, the pair of walls and the more walls collectively completely-encircling an island that includes space between the laterally-spaced walls of the pair of walls and is edge-of-plane.