Pixel-array substrate and defect prevention method
A pixel-array substrate includes a semiconductor substrate and a passivation layer. The semiconductor substrate includes a pixel array surrounded by a periphery region. A back surface of the semiconductor substrate forms, in the periphery region, a plurality of first peripheral-trenches extending into the semiconductor substrate. The passivation layer is on the back surface and lines each of the plurality of first peripheral-trenches.
1. A pixel-array substrate comprising:
a semiconductor substrate including a pixel array surrounded by a periphery region;
a back surface of the semiconductor substrate forming, in the periphery region, a plurality of first peripheral-trenches extending into the semiconductor substrate;
a passivation layer on the back surface and lining each of the plurality of first peripheral-trenches; and
a plurality of inter-column trenches each located between a respective pair of adjacent pixel-columns of the pixel array, each of the plurality of first peripheral-trenches being an extension of a respective one of the plurality of inter-column trenches.
2. The pixel-array substrate of claim 1 ,
a first distance between adjacent inter-column trenches being equal to a distance between adjacent first peripheral-trenches.
3. The pixel-array substrate of claim 1 , each trench of the plurality of first peripheral-trenches having a depth exceeding 0.2 micrometers relative to a planar region of the back surface surrounding the trench.
4. The pixel-array substrate of claim 1 , each trench of the plurality of first peripheral-trenches having a depth, relative to a planar region of the back surface surrounding the trench, that is less than a thickness of the semiconductor substrate by between 0.5 micrometers and 2.0 micrometers.
5. The pixel-array substrate of claim 1 , a thickness of the passivation layer being between 40 angstroms and 500 angstroms.
6. The pixel-array substrate of claim 1 , the passivation layer being formed of a high-κ material.
7. The pixel-array substrate of claim 1 , each of the plurality of first peripheral-trenches having a width between 0.15 micrometers and 0.25 micrometers.
8. The pixel-array substrate of claim 1 , each of the plurality of first peripheral-trenches being filled with an insulating material.
9. The pixel-array substrate of claim 1 ,
the back surface also forming, in the periphery region, a plurality of second peripheral-trenches extending into the semiconductor substrate, each of the plurality of second peripheral-trenches being perpendicular to each of the plurality of first peripheral-trenches,
the passivation layer lining each of the plurality of second peripheral-trenches.
10. The pixel-array substrate of claim 9 , further comprising:
a plurality of inter-row trenches each located between a respective pair of adjacent pixel-rows of the pixel array, a second distance between adjacent inter-row trenches being equal to a distance between adjacent second peripheral-trenches.
11. The pixel-array substrate of claim 10 , each of the plurality of second peripheral-trenches being an extension of a respective one of the plurality of inter-row trenches.
12. The pixel-array substrate of claim 10 , each trench of the plurality of second peripheral-trenches having a depth, relative to a planar region of the back surface surrounding the trench, that is less than a thickness of the semiconductor substrate by between 0.5 micrometers and 2.0 micrometers.
13. The pixel-array substrate of claim 9 , the plurality of a plurality of first peripheral-trenches and the plurality of second peripheral-trenches forming a trench grid structure.
14. An image sensor comprising:
the pixel-array substrate of claim 1 ; and
a microlens array formed of a plurality of microlenses each aligned to a respective photodiode region of the pixel array.
15. The pixel-array substrate of claim 1 , the passivation layer also lining each of the plurality of inter-column trenches.
16. A pixel-array substrate comprising:
a semiconductor substrate including a pixel array surrounded by a periphery region;
a back surface of the semiconductor substrate forming, in the periphery region, a plurality of first peripheral-trenches extending into the semiconductor substrate and being filled with an insulating material; and
a passivation layer on the back surface and lining each of the plurality of first peripheral-trenches.
17. A pixel-array substrate comprising:
a semiconductor substrate having a substrate thickness and including a pixel array surrounded by a periphery region;
a back surface of the semiconductor substrate forming, in the periphery region, a plurality of first peripheral-trenches each extending into the semiconductor substrate, and having a depth, relative to a planar region of the back surface surrounding the trench, that is less than the substrate thickness; and
a passivation layer on the back surface and lining of each of the plurality of first peripheral-trenches.
18. The pixel-array substrate of claim 17 , the depth being less than the substrate thickness between 0.5 micrometers and 2.0 micrometers.
19. The pixel-array substrate of claim 17 , further comprising:
a plurality of second peripheral-trenches each (i) located in the periphery region, (ii) extending into the semiconductor substrate, (iii) being perpendicular to each of the plurality of first peripheral-trenches and (iv) having a depth, relative to a planar region of the back surface surrounding the trench, that is less than the substrate thickness; and
the passivation layer further lining each of the plurality of second peripheral-trenches.
20. The pixel-array substrate of claim 19 ,
the plurality of first peripheral-trenches and the plurality of second peripheral-trenches forming a trench grid structure;
each of the plurality of first peripheral-trenches and the plurality of second peripheral-trenches being filled with an insulating material.