Display panel driven by a thin film transistor including a silicon semiconductor and a thin film transistor including an oxide semiconductor
A display panel includes a substrate, a first thin film transistor including a first semiconductor layer and a first gate electrode, a data line extending in a first direction, a scan line extending in a second direction, a second thin film transistor electrically connected to the data line and including a second semiconductor layer and a second gate electrode, a third thin film transistor including a third semiconductor layer and a first upper gate electrode arranged on the third semiconductor layer, a node connection line electrically connecting the first thin film transistor and the third thin film transistor, and a shield line located between the data line and the node connection line in a plan view and including the same material as the first upper gate electrode of the third thin film transistor. The first semiconductor layer includes a silicon semiconductor, and the third semiconductor layer includes an oxide semiconductor.
1. A display panel comprising:
a substrate;
a first thin film transistor arranged on the substrate and including a first semiconductor layer and a first gate electrode;
a data line arranged on the substrate and extending in a first direction;
a scan line arranged on the substrate and extending in a second direction intersecting the first direction;
a second thin film transistor electrically connected to the data line and including a second semiconductor layer and a second gate electrode;
a third thin film transistor including a third semiconductor layer and a first upper gate electrode arranged on the third semiconductor layer;
a node connection line electrically connecting the first thin film transistor and the third thin film transistor; and
a shield line located between the data line and the node connection line in a plan view, the shield line being arranged on the same layer and including the same material as the first upper gate electrode of the third thin film transistor,
wherein the first semiconductor layer includes a silicon semiconductor and the third semiconductor layer includes an oxide semiconductor.
2. The display panel of claim 1 , further comprising:
a driving voltage line extending in the first direction; and
a horizontal driving voltage line extending in the second direction, partially intersecting the driving voltage line, and electrically connected to the driving voltage line,
wherein the horizontal driving voltage line and the shield line are connected to each other in a same layer.
3. The display panel of claim 1 , wherein the shield line extends in the first direction.
4. The display panel of claim 1 , wherein the shield line intersects the scan line in the plan view.
5. The display panel of claim 1 , wherein the node connection line extends in the first direction and intersects the scan line.
6. The display panel of claim 5 , wherein the node connection line is electrically connected to the third semiconductor layer through a contact hole that is located closer to the first thin film transistor than the scan line in the plan view.
7. The display panel of claim 1 , wherein the first gate electrode has an isolated shape.
8. The display panel of claim 1 , wherein the third thin film transistor further includes a first lower gate electrode arranged under the third semiconductor layer and overlapping the first upper gate electrode, and the first lower gate electrode and the scan line connected to each other in a same layer.
9. The display panel of claim 8 , wherein the first lower gate electrode and the first upper gate electrode include different materials.
10. The display panel of claim 8 , further comprising a fourth thin film transistor including a fourth semiconductor layer and a fourth gate electrode,
wherein the fourth semiconductor layer includes a second oxide semiconductor,
wherein the fourth gate electrode includes:
a second lower gate electrode arranged between the fourth semiconductor layer and the substrate; and
a second upper gate electrode arranged on the fourth semiconductor layer, and
wherein the second upper gate electrode is electrically connected to the second lower gate electrode through a second contact hole that penetrates through at least one insulating layer located between the second upper gate electrode and the second lower gate electrode.
11. A display panel comprising:
a substrate;
a first thin film transistor arranged on the substrate and including a first semiconductor layer and a first gate electrode;
a data line arranged on the substrate and extending in a first direction;
a scan line arranged on the substrate and extending in a second direction that is different from the first direction;
a second thin film transistor electrically connected to the data line and the scan line and including a second semiconductor layer and a second gate electrode; and
a third thin film transistor including a third semiconductor layer including a material that is different from a first material included in the first semiconductor layer and a first upper gate electrode arranged on the third semiconductor layer,
wherein the first upper gate electrode has an isolated shape and is connected to the scan line through a contact hole that penetrates through at least one insulating layer located between the first upper gate electrode and the scan line.
12. The display panel of claim 11 , wherein the scan line is connected to a first lower gate electrode of the third thin film transistor that is located opposite to the first upper gate electrode with the third semiconductor layer located therebetween.
13. The display panel of claim 11 , further comprising a node connection line extending in the first direction and electrically connecting the first thin film transistor and the third thin film transistor.
14. The display panel of claim 13 , wherein the node connection line is electrically connected to the third semiconductor layer through a contact hole that is located closer to the first thin film transistor than the scan line in a plan view.
15. The display panel of claim 13 , further comprising:
a driving voltage line extending in the first direction; and
a shield line electrically connected to the driving voltage line and located between the data line and the node connection line.
16. The display panel of claim 15 , wherein at least a first portion of the shield line and at least a second portion of the driving voltage line are located between the data line and the first upper gate electrode in a plan view.
17. The display panel of claim 15 , wherein the shield line intersects the scan line.
18. The display panel of claim 11 , further comprising a storage capacitor including a first electrode and a second electrode overlapping the first thin film transistor,
wherein the scan line includes a same material as the second electrode of the storage capacitor.
19. The display panel of claim 11 , wherein the first semiconductor layer includes a silicon semiconductor, and
the third semiconductor layer includes an oxide semiconductor.
20. The display panel of claim 11 , further comprising a plurality of insulating layers located between the first semiconductor layer and the third semiconductor layer.