Programmable device having hardened circuits for predetermined digital signal processing functionality
An example programmable device includes a configuration memory configured to store configuration data; a programmable logic having a configurable functionality based on the configuration data in the configuration memory; a signal conversion circuit; a digital processing circuit; an endpoint circuit coupled to the signal conversion circuit through the digital processing circuit; wherein the digital processing circuit includes a first one or more digital processing functions implemented as hardened circuits each having a predetermined functionality, and a second one or more processing functions implemented by the configurable functionality of the programmable logic.
1. An integrated circuit, comprising:
a digital to analog converter (DAC) or analog to digital converter (ADC) circuit;
a digital processing circuit;
a serial transceiver coupled to the DAC or ADC circuit through the digital processing circuit, wherein the digital processing circuit comprises a hardened circuit configured to perform a predetermined functionality, and a programmable subsystem configured to perform a configurable functionality; and
a controller configured to configure the programmable subsystem to perform the configurable functionality.
2. The integrated circuit of claim 1 , wherein the programmable subsystem comprises a digital pre-distortion (DPD) circuit.
3. The integrated circuit of claim 1 , wherein the programmable subsystem comprises an automatic gain control (AGC) circuit.
4. The integrated circuit of claim 1 , wherein the hardened circuit comprises a sample-rate converter.
5. The integrated circuit of claim 1 , wherein the hardened circuit comprises a crest factor reduction (CFR) circuit.
6. The integrated circuit of claim 1 , wherein the hardened circuit and the programmable subsystem are both coupled to an output of the DAC or ADC, wherein the serial transceiver is coupled to outputs of both the hardened circuit and the programmable subsystem.
7. The integrated circuit of claim 1 , wherein the hardened circuit is coupled to an output of the serial transceiver, wherein an input of the programmable subsystem is coupled to an output of the hardened circuit, and wherein an input of the DAC is coupled to an output of the programmable subsystem.
8. The integrated circuit of claim 7 , wherein the hardened circuit comprises a CFR circuit and the programmable subsystem comprises a DPD circuit.
9. The integrated circuit of claim 8 wherein the CFR circuit is directly coupled to the DPD circuit.
10. The integrated circuit of claim 1 , wherein the hardened circuit comprises an interface to the controller.
11. A method, comprising:
transmitting, in an integrated circuit, a signal from a serial transceiver to a digital processing circuit;
processing the signal using the digital processing circuit, wherein the digital processing circuit comprises a hardened circuit configured to perform a predetermined functionality, and a programmable subsystem configured to perform a configurable functionality;
configuring the programmable subsystem to perform the configurable functionality; and
transmitting the signal from the digital processing circuit to a digital to analog converter (DAC).
12. The method of claim 11 , wherein the programmable subsystem comprises a digital pre-distortion (DPD) circuit.
13. The method of claim 11 , wherein the programmable subsystem comprises an automatic gain control (AGC) circuit.
14. The method of claim 11 , wherein the hardened circuit comprises a sample-rate converter.
15. The method of claim 11 , wherein the hardened circuit comprises a crest factor reduction (CFR) circuit.
16. The method of claim 11 , wherein the hardened circuit and the programmable subsystem are both coupled to an output of the DAC or an ADC, wherein the serial transceiver is coupled to outputs of both the hardened circuit and the programmable subsystem.
17. The method of claim 11 , wherein the hardened circuit is coupled to an output of the serial transceiver, wherein an input of the programmable subsystem is coupled to an output of the hardened circuit, and wherein an input of the DAC is coupled to an output of the programmable subsystem.
18. The method of claim 17 , wherein the hardened circuit comprises a CFR circuit and the programmable subsystem comprises a DPD circuit.
19. The method of claim 18 , wherein the CFR circuit is directly coupled to the DPD circuit.
20. The method of claim 11 , wherein the hardened circuit comprises an interface to a controller that configures the programmable subsystem to perform the configurable functionality.