Fault tolerant computation method and apparatus for quantum Clifford circuit, device, and chip

1. A fault tolerant computation method for a quantum Clifford circuit, the method comprising:

decomposing a quantum Clifford circuit into s logic Clifford circuits, s being a positive integer;

preparing auxiliary quantum states corresponding to the s logic Clifford circuits; and

for an i th logic Clifford circuit of the s logic Clifford circuits, i being a positive integer less than or equal to s:

teleporting an input quantum state corresponding to the i th logic Clifford circuit to an auxiliary qubit corresponding to the i th logic Clifford circuit;

processing a quantum state obtained after the teleportation by the i th logic Clifford circuit to obtain an output quantum state corresponding to the i th logic Clifford circuit;

measuring an error symptom corresponding to the i th logic Clifford circuit based on the input quantum state and the auxiliary quantum state that correspond to the i th logic Clifford circuit during the teleportation; and

performing error correction on the output quantum state corresponding to the i th logic Clifford circuit according to the error symptom corresponding to the i th logic Clifford circuit, to obtain an error-corrected output quantum state.

2. The method according to claim 1 , wherein measuring the error symptom corresponding to the i th logic Clifford circuit based on the input quantum state and the auxiliary quantum state that correspond to the i th logic Clifford circuit comprises:

processing the input quantum state and the auxiliary quantum state that correspond to the i th logic Clifford circuit by using a controlled NOT (CNOT) gate;

measuring a physical qubit corresponding to the input quantum state in Pauli-Z direction, and measuring a physical qubit corresponding to the auxiliary quantum state in Pauli-X direction, to obtain a measurement result; and

determining the error symptom corresponding to the i th logic Clifford circuit based on the measurement result.

3. The method according to claim 2 , wherein performing the error correction on the output quantum state corresponding to the i th logic Clifford circuit according to the error symptom corresponding to the i th logic Clifford circuit, to obtain the error-corrected output quantum state comprises:

determining, based on the measurement result, a logic Pauli-X operator and a logic Pauli-Z operator that need to be error-corrected;

determining an occurrence position and a type of an error based on the error symptom corresponding to the i th logic Clifford circuit and by using a decoding algorithm corresponding to a quantum error correction (QEC) code; and

performing the error correction on the output quantum state corresponding to the i th logic Clifford circuit to obtain the error-corrected output quantum state after the logic Pauli-X operator and the logic Pauli-Z operator that need to be error corrected are corrected.

4. The method according to claim 1 , wherein preparing the auxiliary quantum states corresponding to the s logic Clifford circuits comprises:

determining the auxiliary quantum states corresponding to the s logic Clifford circuits;

building fault tolerant preparation circuits corresponding to the auxiliary quantum states; and

preparing the auxiliary quantum states by using the fault tolerant preparation circuits in parallel in a pipelined manner.

5. The method according to claim 1 , wherein s is less than or equal to 9.

6. The method according to claim 1 , wherein the i th logic Clifford circuit comprises a single-type gate, and the single-type gate comprises any one of a controlled NOT (CNOT) gate, a Hadamard gate, or a phase gate.

7. The method according to claim 6 , wherein the auxiliary quantum state corresponding to the i th logic Clifford circuit comprises at least one of the following: an auxiliary quantum state corresponding to the CNOT gate, an auxiliary quantum state corresponding to the Hadamard gate, and an auxiliary quantum state corresponding to the phase gate.

8. The method according to claim 1 , wherein decomposing the quantum Clifford circuit into s logic Clifford circuits comprises:

transforming the quantum Clifford circuit into a form of a symplectic matrix to obtain a symplectic matrix representation of the quantum Clifford circuit; and

decomposing the symplectic matrix representation of the quantum Clifford circuit to obtain symplectic matrix representations of the s logic Clifford circuits.

9. A fault tolerant computation device for a quantum Clifford circuit comprising a memory for storing instructions and a processor for executing the instructions to:

decompose a quantum Clifford circuit into s logic Clifford circuits, s being a positive integer;

prepare auxiliary quantum states corresponding to the s logic Clifford circuits; and

for an i th logic Clifford circuit of the s logic Clifford circuits corresponding to the i th logic Clifford circuit, i being a positive integer less than or equal to s:

teleport an input quantum state corresponding to the i th logic Clifford circuit to an auxiliary qubit;

process a quantum state obtained after the teleportation by the i th logic Clifford circuit to obtain an output quantum state corresponding to the i th logic Clifford circuit;

measure an error symptom corresponding to the i th logic Clifford circuit based on the input quantum state and the auxiliary quantum state that correspond to the i th logic Clifford circuit during the teleportation; and

perform error correction on the output quantum state corresponding to the i th logic Clifford circuit according to the error symptom corresponding to the i th logic Clifford circuit, to obtain an error-corrected output quantum state.

10. The fault tolerant computation device according to claim 9 , wherein to measure the error symptom corresponding to the i th logic Clifford circuit based on the input quantum state and the auxiliary quantum state that correspond to the i th logic Clifford circuit, the processor is configured to execute the instructions to:

process the input quantum state and the auxiliary quantum state that correspond to the i th logic Clifford circuit by using a controlled NOT (CNOT) gate;

measure a physical qubit corresponding to the input quantum state in Pauli-Z direction, and measuring a physical qubit corresponding to the auxiliary quantum state in Pauli-X direction, to obtain a measurement result; and

determine the error symptom corresponding to the i th logic Clifford circuit based on the measurement result.

11. The fault tolerant computation device according to claim 10 , wherein to perform the error correction on the output quantum state corresponding to the i th logic Clifford circuit according to the error symptom corresponding to the i th logic Clifford circuit, to obtain the error-corrected output quantum state, the processor is configured to execute the instructions to:

determine, based on the measurement result, a logic Pauli-X operator and a logic Pauli-Z operator that need to be error-corrected;

determine an occurrence position and a type of an error based on the error symptom corresponding to the i th logic Clifford circuit and by using a decoding algorithm corresponding to a quantum error correction (QEC) code; and

perform the error correction on the output quantum state corresponding to the i th logic Clifford circuit to obtain the error-corrected output quantum state after the logic Pauli-X operator and the logic Pauli-Z operator that need to be error corrected are corrected.

12. The fault tolerant computation device according to claim 9 , wherein to prepare the auxiliary quantum states corresponding to the s logic Clifford circuits, the processor is configured to execute the instructions to:

determine the auxiliary quantum states corresponding to the s logic Clifford circuits;

build fault tolerant preparation circuits corresponding to the auxiliary quantum states; and

prepare the auxiliary quantum states by using the fault tolerant preparation circuits in parallel in a pipelined manner.

13. The fault tolerant computation device according to claim 9 , wherein s is less than or equal to 9.

14. The fault tolerant computation device according to claim 9 , wherein the i th logic Clifford circuit comprises a single-type gate, and the single-type gate comprises any one of a controlled NOT (CNOT) gate, a Hadamard gate, or a phase gate.

15. The fault tolerant computation device according to claim 14 , wherein the auxiliary quantum state corresponding to the i th logic Clifford circuit comprises at least one of the following: an auxiliary quantum state corresponding to the CNOT gate, an auxiliary quantum state corresponding to the Hadamard gate, and an auxiliary quantum state corresponding to the phase gate.

16. The fault tolerant computation device according to claim 9 , wherein to decompose the quantum Clifford circuit into s logic Clifford circuits, the processor is configured to execute the instructions to:

transform the quantum Clifford circuit into a form of a symplectic matrix to obtain a symplectic matrix representation of the quantum Clifford circuit; and

decompose the symplectic matrix representation of the quantum Clifford circuit to obtain symplectic matrix representations of the s logic Clifford circuits.

17. The fault tolerant computation device according to claim 9 , wherein the processor comprises a superconducting quantum computation (QC) chip.

18. The fault tolerant computation device according to claim 17 , wherein:

the superconducting QC chip comprises m layer of physical qubits having a three-dimensional integrated packaging, m being an integer greater than 1;

each layer of physical qubits being used for forming a quantum state, the quantum state comprising any one of the input quantum state, the auxiliary quantum state, and the output quantum state; and

physical qubits at the same position in different layers are coupled by a data bus.

19. The fault tolerant computation device of claim 18 , wherein for the physical qubits at the same position in different layers, the data bus is formed by using a deep through-silicon via technology to couple the physical qubits.

20. A non-transitory computer-readable storage medium, storing at least one instruction, at least one program, a code set or an instruction set, and the at least one instruction, the at least one program, the code set or the instruction set, when being loaded and executed by a processor, is configure to cause the processor to:

decompose a quantum Clifford circuit into s logic Clifford circuits, s being a positive integer;

prepare auxiliary quantum states corresponding to the s logic Clifford circuits; and

for an i th logic Clifford circuit of the s logic Clifford circuits corresponding to the i th logic Clifford circuit, i being a positive integer less than or equal to s:

teleport an input quantum state corresponding to the i th logic Clifford circuit to an auxiliary qubit;

process a quantum state obtained after the teleportation by the i th logic Clifford circuit to obtain an output quantum state corresponding to the i th logic Clifford circuit;

measure an error symptom corresponding to the i th logic Clifford circuit based on the input quantum state and the auxiliary quantum state that correspond to the i th logic Clifford circuit during the teleportation; and

perform error correction on the output quantum state corresponding to the i th logic Clifford circuit according to the error symptom corresponding to the i th logic Clifford circuit, to obtain an error-corrected output quantum state.