Trigger activation by repeated maximal clique sampling

1. A method comprising:

obtaining, by a computing device, a design graph representation of an electronic circuit;

constructing, by the computing device, a satisfiability graph from the design graph representation, wherein the satisfiability graph includes a set of vertices representing rare signals of the electronic circuit and satisfiability connections between the vertices;

finding, by the computing device, a plurality of maximal satisfiable cliques in the satisfiability graph, wherein a maximal satisfiable clique corresponds to a triggering condition for a payload of the electronic circuit;

generating, by the computing device, a test vector for each of the maximal satisfiable cliques; and

performing, by the computing device, a test for a presence of a hardware Trojan circuit in the electronic circuit using the generated test vectors as input signals.

2. The method of claim 1 , further comprising generating the design graph representation from a gate-level netlist for the electronic circuit.

3. The method of claim 1 , wherein the plurality of maximal satisfiable cliques is all of the maximal satisfiable cliques in the satisfiability graph.

4. The method of claim 1 , wherein the plurality of maximal satisfiable cliques is a subset of the maximal satisfiable cliques in the satisfiability graph.

5. The method of claim 4 , wherein the plurality of maximal satisfiable cliques is found by a random sampling of valid trigger conditions that enable the payload of the electronic circuit.

6. The method of claim 4 , wherein the plurality of maximal satisfiable cliques is found by a biased sampling of valid trigger conditions that enable the payload of the electronic circuit.

7. The method of claim 1 , wherein an satisfiability solver is utilized to generate the test vector for each of the maximal satisfiable cliques.

8. The method of claim 1 , wherein constructing the satisfiability graph comprises transforming the design graph representation to the satisfiability graph using a rareness threshold.

9. The method of claim 8 , further comprising simulating the electronic circuit using random test vectors to record a number of times a signal output is generated; and determining a signal output to be a rare signal output when the signal output satisfies a specific value below the rareness threshold.

10. The method of claim 1 , wherein the vertices of a particular maximal satisfiable clique are activated by application of a test vector corresponding to the maximal satisfiable clique to the electronic circuit.

11. A system comprising:

one or more computing processors; and

one or more memory storage elements;

wherein the one or more computing processors are configured to:

obtain a design graph representation of an electronic circuit;

construct a satisfiability graph from the design graph representation, wherein the satisfiability graph includes a set of vertices representing rare signals of the electronic circuit and satisfiability connections between the vertices;

find a plurality of maximal satisfiable cliques in the satisfiability graph, wherein a maximal satisfiable clique corresponds to a triggering condition for a payload of the electronic circuit;

generate a test vector for each of the maximal satisfiable cliques; and

perform a test for a presence of a hardware Trojan circuit in the electronic circuit using the generated test vectors as input signals.

12. The system of claim 11 , wherein the one or more computing processors are further configured to generate the design graph representation from a gate-level netlist for the electronic circuit.

13. The system of claim 11 , wherein the plurality of maximal satisfiable cliques is all of the maximal satisfiable cliques in the satisfiability graph.

14. The system of claim 11 , wherein the plurality of maximal satisfiable cliques is a subset of the maximal satisfiable cliques in the satisfiability graph, wherein the plurality of maximal satisfiable cliques is found by a random sampling of valid trigger conditions that enable a payload of the electronic circuit.

15. The system of claim 11 , wherein the plurality of maximal satisfiable cliques is a subset of the maximal satisfiable cliques in the satisfiability graph, wherein the plurality of maximal satisfiable cliques is found by a biased sampling of valid trigger conditions that enable a payload of the electronic circuit.

16. The system of claim 11 , wherein an satisfiability solver is utilized to generate the test vector for each of the maximal satisfiable cliques.

17. The system of claim 11 , wherein constructing the satisfiability graph comprises transforming the design graph representation to the satisfiability graph using a rareness threshold.

18. The system of claim 17 , wherein the one or more computing processors are further configured to simulate the electronic circuit using random test vectors to record a number of times a signal output is generated; and determining a signal output to be a rare signal output when the signal output satisfies a specific value below the rareness threshold.

19. The system of claim 11 , wherein the vertices of a particular maximal satisfiable clique are activated by application of a test vector corresponding to the maximal satisfiable clique to the electronic circuit.

20. A non-transitory computer-readable medium having instructions stored thereon that, in response to execution by a computer-based system, cause the computer-based system to perform operations comprising:

obtaining a design graph representation of an electronic circuit;

constructing a satisfiability graph from the design graph representation, wherein the satisfiability graph includes a set of vertices representing rare signals of the electronic circuit and satisfiability connections between the vertices;

finding a plurality of maximal satisfiable cliques in the satisfiability graph, wherein a maximal satisfiable clique corresponds to a triggering condition for a payload of the electronic circuit;

generating a test vector for each of the maximal satisfiable cliques; and

performing a test for a presence of a hardware Trojan circuit in the electronic circuit using the generated test vectors as input signals.