FinFET semiconductor device grouping

1. A method of designing a circuit, comprising:

providing a static random-access memory (SRAM) circuit including a memory cell and a write driver, both the memory cell and the write driver coupled between a first bit line and a second bit line;

selecting a first NMOS fin field-effect transistor (FinFET) in the circuit; and

replacing the first NMOS FinFET having a first fin number with a second NMOS FinFET having a second fin number and a third NMOS FinFET having a third fin number, wherein the sum of the second fin number and the third fin number is equal to the first fin number;

wherein the write driver comprises:

a first PMOS FinFET having a first source/drain terminal coupled to a first power terminal;

a second PMOS FinFET having a first source/drain terminal coupled to a second source/drain terminal of the first PMOS FinFET, and a gate terminal coupled to the first bit line;

a third PMOS FinFET having a first source/drain terminal coupled to the first power terminal;

a fourth PMOS FinFET having a first source/drain terminal coupled to a second source/drain terminal of the third PMOS FinFET, and a gate terminal coupled to the second bit line;

the first NMOS FinFET connected between a second source/drain terminal of the second PMOS FinFET and a second power terminal, wherein a gate terminal of the first NMOS FinFET is connected to a first write input terminal; and

a fourth NMOS FinFET connected between a second source/drain terminal of the fourth PMOS FinFET and a second power terminal, wherein a gate terminal of the fourth NMOS FinFET is connected to a second write input terminal.

2. The method of claim 1 , further comprising:

selecting a first PMOS FinFET and a second PMOS FinFET in the circuit; and

replacing the first PMOS FinFET having a fourth fin number and the second PMOS FinFET having a fifth fin number with a third PMOS FinFET having a sixth fin number, wherein the sum of the fourth fin number and the fifth fin number is equal to the sixth fin number.

3. A method of designing a circuit, comprising:

providing a circuit;

determining a first number of fins for a first PMOS FinFET in the circuit based on a first criterion;

determining a second number of fins for a second PMOS FinFET in the circuit based on the first criterion;

replacing the first PMOS FinFET having the first number of fins and the second PMOS FinFET having the second number of fins with a third PMOS FinFET having a third number of fins based on a second criterion, wherein the sum of the first number of fins and the second number of fins is equal to the third number of fins;

determining a fourth number of fins for a first NMOS FinFET in the circuit based on the first criterion;

replacing the first NMOS FinFET having the fourth number of fins with a second NMOS FinFET having a fifth number of fins and a third NMOS FinFET having a sixth number of fins based on the second criterion, wherein the sum of the fifth number of fins and the sixth number of fins is equal to the fourth number of fins.

4. The method of claim 3 , the first PMOS FinFET and the second PMOS FinFET are connected in parallel.

5. The method of claim 3 , wherein the providing a circuit includes providing a SRAM circuit, and the SRAM circuit comprises a memory cell and a first header circuit connected between the memory cell and a first voltage terminal, wherein the first header circuit comprises the first PMOS FinFET and the second PMOS FinFET connected in parallel, and the first PMOS FinFET and the second PMOS FinFET are turned on or turned off in response to a shutdown signal.

6. The method of claim 3 , wherein the providing a circuit includes providing an inverter circuit having the first PMOS FinFET and the second PMOS FinFET connected in parallel.

7. An SRAM device, comprising:

a memory cell including:

a first inverter;

a second inverter cross-coupled to the first inverter;

a first access transistor connected between a first data node of the first inverter and a first bit line; and

a second access transistor connected between a second data node of the second inverter and a second bit line; and

a write driver including:

a first PMOS FinFET having a first source/drain terminal coupled to a first power terminal;

a second PMOS FinFET having a first source/drain terminal coupled to a second source/drain terminal of the first PMOS FinFET, and a gate terminal coupled to the first bit line;

a third PMOS FinFET having a first source/drain terminal coupled to the first power terminal;

a fourth PMOS FinFET having a first source/drain terminal coupled to a second source/drain terminal of the third PMOS FinFET, and a gate terminal coupled to the second bit line;

first and second NMOS FinFETs connected in parallel between a second source/drain terminal of the second PMOS FinFET and a second power terminal, wherein a gate terminal of the first PMOS FinFET and gate terminals of the first and second NMOS FinFETs are connected to receive a first write signal; and

third and fourth NMOS FinFETs connected in parallel between a second source/drain terminal of the fourth PMOS FinFET and the second power terminal, wherein a gate terminal of the third PMOS FinFET and gate terminals of the third and fourth NMOS FinFETs are connected to receive a second write signal.

8. The SRAM device of claim 7 , wherein the first and second NMOS FinFETs together have a first number of fins, the first and second NMOS FinFETs replacing a first single NMOS FinFET having the first number of fins, and wherein the third and fourth NMOS FinFETs together have the first number of fins, the third and fourth NMOS FinFETs replacing a second single NMOS FinFET having the first number of fins.

9. The method of claim 3 , wherein the first criterion includes a saturation current (Idsat).

10. The method of claim 9 , wherein the first criterion includes a turning-speed.

11. The method of claim 9 , wherein the second criterion includes a leakage current (Ioff) at an off state.

12. The method of claim 3 , wherein the circuit is a logic circuit.

13. The method of claim 3 , wherein the circuit is an analog circuit.

14. The method of claim 3 , wherein the circuit includes an inverter circuit having the third PMOS FinFET connected in series with the third NMOS FinFET between a first power terminal and a second power terminal.

15. The method of claim 3 , wherein the circuit includes a word line driver of a memory device, and the word line driver comprises a first inverter and a second inverter connected in series between a clock signal terminal and a word line signal terminal.

16. The method of claim 15 , wherein the second inverter comprises the third NMOS FinFET.

17. The method of claim 3 , wherein the circuit includes a decoder driver of a memory device, and the decoder driver comprises a NAND gate and an inverter connected in series between two input signal terminals and an output terminal.

18. The method of claim 17 , wherein the inverter comprises the third NMOS FinFET.

19. The method of claim 3 , wherein,

the first PMOS FinFET includes a gate finger extending over the first number of fins;

the second PMOS FinFET includes the gate finger extending over the second number of fins; and

the third PMOS FinFET includes the gate finger extending over the third number of fins.

20. The method of claim 3 , wherein:

the first NMOS FinFET includes a gate finger extending over the fourth number of fins;

the second NMOS FinFET includes the gate finger extending over the fifth number of fins; and

the third NMOS FinFET includes the gate finger extending over the sixth number of fins.