Pixel circuit and display device including the same
A pixel circuit includes first to fifth transistors, a capacitor, and a light emitting element. The first transistor is coupled between first and second power lines, and includes a gate electrode coupled to a first node and a back-gate electrode coupled to a second node. The second transistor is coupled between a data line and the first node, and includes a gate electrode coupled to a first scan line. The third transistor is coupled between a third power line and the first node, and includes a gate electrode coupled to a reference scan line. The fourth transistor is coupled between a second node and a fourth power line, and includes a gate electrode coupled to a second scan line. The fifth transistor is coupled between a first power line and the one electrode of the first transistor, and includes a gate electrode coupled to a light-emitting control line.
1. A pixel circuit comprising:
a first transistor including a first electrode, a second electrode coupled to a second node, a gate electrode coupled to a first node, and a bottom electrode directly coupled to the second node;
a second transistor including a first electrode coupled to a data line, a second electrode coupled to the first node, and a gate electrode coupled to a first scan line;
a third transistor including a first electrode coupled to a third power line, a second electrode coupled to the first node, and a gate electrode coupled to a reference scan line;
a fourth transistor including a first electrode coupled to the second node, a second electrode coupled to a fourth power line, and a gate electrode coupled to a second scan line;
a fifth transistor including a first electrode coupled to a first power line, a second electrode coupled to the first electrode of the first transistor, and a gate electrode coupled to a light-emitting control line; and
a light emitting element coupled to the second node and a second power line.
2. The pixel circuit according to claim 1 , wherein the bottom electrode of the first transistor is disposed to overlap the gate electrode of the first transistor with an insulating layer interposed therebetween.
3. The pixel circuit according to claim 2 , wherein each of the first to fourth transistors comprises an oxide semiconductor, and
the fifth transistor comprises a silicon semiconductor.
4. The pixel circuit according to claim 3 , wherein the gate electrode of each of the first to fifth transistors is disposed on a semiconductor.
5. The pixel circuit according to claim 4 , wherein the bottom electrode of the first transistor and the gate electrode of the fifth transistor are disposed on the same layer.
6. The pixel circuit according to claim 2 , wherein the second transistor further comprises a bottom electrode coupled to the gate electrode of the second transistor.
7. The pixel circuit according to claim 6 , wherein the third transistor further comprises a bottom electrode coupled to the gate electrode of the third transistor.
8. The pixel circuit according to claim 7 , wherein the fourth transistor further comprises a bottom electrode coupled to the gate electrode of the fourth transistor.
9. The pixel circuit according to claim 1 , further comprising:
a capacitor coupled between the second node and the first node.
10. A display device comprising:
a display including a first power line, a second power line, a third power line, a fourth power line, a data line, a first scan line, a second scan line, a reference scan line, a light-emitting control line, and a pixel;
a data driver configured to supply a data signal to the data line; and
a gate driver configured to sequentially supply a first gate signal to the second scan line and the first scan line, to supply a second gate signal to the reference scan line, and to supply a third gate signal to the light-emitting control line,
wherein the pixel comprises:
a first transistor including a first electrode, a second electrode coupled to a second node, a gate electrode coupled to a first node, a bottom electrode directly coupled to the second node;
a second transistor including a first electrode coupled to the data line, a second electrode coupled to the first node, and a gate electrode coupled to the first scan line;
a third transistor including a first electrode coupled to the third power line, a second electrode coupled to the first node, and a gate electrode coupled to the reference scan line;
a fourth transistor including a first electrode coupled to the second node, a second electrode coupled to the fourth power line, and a gate electrode coupled to the second scan line;
a fifth transistor including a first electrode coupled to the first power line, a second electrode coupled to the first electrode of the first transistor, and a gate electrode coupled to the light-emitting control line; and
a light emitting element coupled to the second node and the second power line.
11. The display device according to claim 10 , wherein the second transistor further comprises a bottom electrode coupled to the gate electrode of the second transistor.
12. The display device according to claim 11 , wherein the third transistor further comprises a bottom electrode coupled to the gate electrode of the third transistor.
13. The display device according to claim 12 , wherein the fourth transistor further comprises a bottom electrode coupled to the gate electrode of the fourth transistor.
14. The display device according to claim 10 , further comprising:
a capacitor coupled between the second node and the first node.
15. The display device according to claim 14 , wherein, in a first section, the gate driver supplies the second gate signal having a turn-on voltage level to the reference scan line, and supplies the first gate signal having a turn-on voltage level to the second scan line.
16. The display device according to claim 15 , wherein, in a second section, the gate driver supplies the third gate signal having a turn-on voltage level to the light-emitting control line, and supplies the first gate signal having a turn-off voltage level to the second scan line, and
wherein the second section is different from the first section and is longer than the first section.
17. The display device according to claim 16 , wherein, in a third section, the gate driver supplies the first gate signal having the turn-on voltage level to the first scan line, and
wherein the third section is different from the first and second sections and has the same width as that of the first section.
18. The display device according to claim 17 , wherein, in a fourth section, the gate driver supplies the third gate signal having the turn-on voltage level to the light-emitting control line, and the light emitting element emits light at a luminance corresponding to the data signal.
19. The display device according to claim 18 , wherein the first to fourth sections are included in a first frame,
wherein the second to fourth transistors maintain a turn-off state in a second frame subsequent to the first frame, and
wherein a first period when the fifth transistor is turned off in the second frame is longer than a second period when the fifth transistor is turned off in the first frame.
20. The display device according to claim 19 , wherein a period when the light emitting element emits light in the second frame is substantially the same as a period when the light emitting element emits light in the first frame.